Abstract: A method for preparing a polymeric material includes: providing a polymeric matrix having at least one polymer and at least one porogen; and degrading the at least one porogen at a temperature T?1.1 Tg, where Tg is a glass transition temperature of the polymeric matrix. The degrading step includes exposing the polymeric matrix to thermal degradation, chemical degradation, electrical degradation and/or radiation degradation, wherein the polymeric material has a permeability at least 1.2 times a permeability of the polymeric matrix for a gas, and a selectivity of the polymeric material is at least 0.35 times a selectivity of the polymeric matrix for a gas pair. The method preferably provides gas separation membranes that exceed Robeson's upper bound relationship for at least one gas separation pair. Novel polymeric materials, gas separation membranes and fluid component separation methods are also described.

Abstract: A method for preparing a polymeric material includes: providing a polymeric matrix having at least one polymer and at least one porogen; and degrading the at least one porogen at a temperature T?1.1 Tg, where Tg is a glass transition temperature of the polymeric matrix. The degrading step includes exposing the polymeric matrix to thermal degradation, chemical degradation, electrical degradation and/or radiation degradation, wherein the polymeric material has a permeability at least 1.2 times a permeability of the polymeric matrix for a gas, and a selectivity of the polymeric material is at least 0.35 times a selectivity of the polymeric matrix for a gas pair. The method preferably provides gas separation membranes that exceed Robeson's upper bound relationship for at least one gas separation pair. Novel polymeric materials, gas separation membranes and fluid component separation methods are also described.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.

Abstract: This invention pertains to alkyl substituted difunctional cyclohexylisocyanates having an isomer distribution. The isocyanates are represented by the formulas: ##STR1## wherein; R.sup.1 is C.sub.1-4 alkyl; R.sup.2 is C.sub.1-4 alkyl andn is 0 or 2.The invention also relates to polyurethane and polyurethane/urea resins prepared using the alkyl substituted difunctional cyclohexylisocyanates as at least a portion of the polyisocyanate used in forming the polyurethane.

Abstract: This invention relates to polyurethane coatings formed from prepolymers made by reacting polyisocyanates with long chain polyols having an average functionality of greater than 2. The resulting prepolymers have equivalent weights greater than about 250 grams per equivalent and preferably greater than about 350 grams per equivalent. An excess of polyisocyanate is reacted with the polyol component at an equivalent ratio of greater than 4:1 equivalents isocyanate per equivalent of polyol. Excess polyisocyanate is then removed from the prepolymer.The resulting polyurethane prepolymers are chain extended with compounds having active hydrogen atoms such as water, amines or short chain polyhydroxy compounds, e.g., diols to form the resulting coatings.

Abstract: This invention relates to a polyisocyanate prepolymer for polyurethane and polyurethane/urea elastomer synthesis and to the resulting elastomer. The prepolymer is formed by reacting a cyclohexanediisocyanate with a long chain polyol under conditions such that essentially a 2:1 adduct is formed. Excess cyclohexanediisocyanate is removed prior to forming the elastomer.