Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines is provided. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for register renaming allows processor hardware to use a larger set of registers than the architected registers visible to the compiler. This larger set of registers is called the physical register file. Thus, dynamically renaming every compiler-suggested architected register to a microarchitecture-specific physical register, allows the processor to overcome name dependencies and the hazards (pipeline slowdowns) induced by name dependencies.

Abstract: A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

Abstract: A system for employing a scalable distributed arbitration scheme, including: a plurality of stations interconnected via a ring topology for transferring data between the plurality of stations; and a bus coupling the plurality of stations in the ring topology; wherein each of the plurality of stations on the topology ring is permitted to independently make a decision when to load their data on the topology ring by evaluating a set of inputs.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Abstract: Register renaming as contemplated by this invention allows processor hardware to use a larger set of registers than the architected registers visible to the compiler. This larger set of registers is called the physical register file. Thus, dynamically renaming every compiler-suggested architected register to a microarchitecture-specific physical register, allows the processor to overcome name dependencies and the hazards (pipeline slowdowns) induced by name dependencies. The invention here described differs from prior renaming techniques in that it extracts significant benefit from renaming with a fraction of the number of physical registers previously used for this process. The invention therefore also simplifies the logic involved in supporting the use of the physical registers.

Abstract: A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

Abstract: In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.