Abstract: Mounting hardware is installed to a cryogenic storage device to accommodate an automation system for automated storage and retrieval. A guideplate at an upper surface of a cover of the cryogenic storage device is positioned such that the guideplate is aligned in a predefined relation to an access port at the upper surface. One or more mounting posts are affixed at a location as indicated by the guideplate. A vacuum is then pulled within the cover, and the mounting hardware is affixed to the at least one mounting post.

Abstract: A configurable cryogenic storage device has a freezer and a rack carrier positioned inside of the freezer. The freezer includes a bearing and a drive shaft though the freezer, the drive shaft being coupled to the rack carrier inside the freezer and adapted to be coupled to a motor assembly. The rack carrier rests on the bearing in a manual rotation configuration and hangs from the drive shaft when the motor is connected. Coupling the drive shaft to the motor assembly lifts the rack carrier and decouples the bearing and enables automated rotation of the rack carrier by the motor. The rack carrier includes rack-mounting features holding a plurality of sample storage racks. The sample storage racks hang from the rack carrier and the rack-mounting features precisely position the end of each sample storage rack.

Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Abstract: Approaches are described to improve database performance by implementing a RLE decompression function at a low level within a general-purpose processor or an external block. Specifically, embodiments of a hardware implementation of an instruction for RLE decompression are disclosed. The described approaches improve performance by supporting the RLE decompression function within a processor and/or external block. Specifically, a RLE decompression hardware implementation is disclosed that produces a 64-bit RLE decompression result, with an example embodiment performing the task in two pipelined execution stages with a throughput of one per cycle. According to embodiments, hardware organization of narrow-width shifters operating in parallel, controlled by computed shift counts, is used to perform the decompression.

Abstract: Methods for the treatment of peripheral neuropathy are provided which include applying a topical composition to a peripheral appendage of a subject in need of such treatment. The topical composition includes a B1 vitamer, a B6 vitamer, and a B9 vitamer in a dermatologically acceptable carrier. The methods are effective in preventing further degeneration and/or restoring epidermal nerve fiber density (ENFD) in patients with peripheral neuropathy, and in preventing or alleviating neuropathic pain.

Abstract: A configurable cryogenic storage device has a freezer and a rack carrier positioned inside of the freezer. The freezer includes a bearing and a drive shaft though the freezer, the drive shaft being coupled to the rack carrier inside the freezer and adapted to be coupled to a motor assembly. The rack carrier rests on the bearing in a manual rotation configuration and hangs from the drive shaft when the motor is connected. Coupling the drive shaft to the motor assembly lifts the rack carrier and decouples the bearing and enables automated rotation of the rack carrier by the motor. The rack carrier includes rack-mounting features holding a plurality of sample storage racks. The sample storage racks hang from the rack carrier and the rack-mounting features precisely position the end of each sample storage rack.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract: The disclosed embodiments relate to the design of an integer division circuit, which comprises: a dividend-input that receives an integer dividend A; a divisor-input that receives an integer divisor B; a quotient-output that outputs an integer quotient q; and a division engine that executes the Goldschmidt method to divide A by B to produce q. During a pre-processing operation, which commences executing before the Goldschmidt method starts executing, the division engine determines whether A<B. If A<B, the division engine sets q=0 without having to execute the Goldschmidt method.

Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract: A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.

Abstract: A configurable cryogenic storage device has a freezer and a rack carrier positioned inside of the freezer. The freezer includes a bearing and a drive shaft though the freezer, the drive shaft being coupled to the rack carrier inside the freezer and adapted to be coupled to a motor assembly. The rack carrier rests on the bearing in a manual rotation configuration and hangs from the drive shaft when the motor is connected. Coupling the drive shaft to the motor assembly lifts the rack carrier and decouples the bearing and enables automated rotation of the rack carrier by the motor. The rack carrier includes rack-mounting features holding a plurality of sample storage racks. The sample storage racks hang from the rack carrier and the rack-mounting features precisely position the end of each sample storage rack.

Abstract: Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (IRF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution unit, a working register file (WRF), an FRF, and an IRF. To achieve the single cycle movement functionality, the integer execution unit may physically own the WRF, IRF, and FRF, and may monitor and control any dependencies between them. Thus, since the integer execution unit has direct read access to both the IRF and the FRF, data may be moved between the two register files using the single cycle operation of the integer execution unit, without the need to store and load the data from memory.

Abstract: Approaches are described to improve database performance by implementing a RLE decompression function at a low level within a general-purpose processor or an external block. Specifically, embodiments of a hardware implementation of an instruction for RLE decompression are disclosed. The described approaches improve performance by supporting the RLE decompression function within a processor and/or external block. Specifically, a RLE decompression hardware implementation is disclosed that produces a 64-bit RLE decompression result, with an example embodiment performing the task in two pipelined execution stages with a throughput of one per cycle. According to embodiments, hardware organization of narrow-width shifters operating in parallel, controlled by computed shift counts, is used to perform the decompression.