Patents by Inventor Jeffrey S. Conger

Jeffrey S. Conger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8885357
    Abstract: A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: November 11, 2014
    Assignee: Cray Inc.
    Inventors: Hyunjun Kim, Jeffrey S. Conger, Gregory E. Scott
  • Publication number: 20130175077
    Abstract: A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Inventors: Hyunjun Kim, Jeffrey S. Conger, Gregory E. Scott
  • Patent number: 6726505
    Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 27, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Stephen Cermak, III, Jeffrey S. Conger, David Paul Gruber, Thomas Alex Crapisi, Stephen A. Bowen, Steven Shafer, Mark Ronald Sikkink
  • Publication number: 20030077925
    Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.
    Type: Application
    Filed: August 29, 2002
    Publication date: April 24, 2003
    Applicant: Silicon Graphics, Inc.
    Inventors: Stephen Cermak, Jeffrey S. Conger, David Paul Gruber, Thomas Alex Crapisi, Stephen A. Bowen, Steven Shafer, Mark Ronald Sikkink
  • Patent number: 6487082
    Abstract: A printed circuit board apparatus, configurations and methods are presented which provide for close spacing between the HUB and multiple processors as well as a common configuration for two or four processor boards. A printed circuit board is provided with conductive apertures and portions corresponding to an efficient Packaging allowing for the attachment of the processor-chip on one side of the printed circuit board, and the HUB and other supporting electronic components on the other side of the printed circuit board. This configuration allows for the close spacing of the electrical conductors of the HUB and the processors without the limitations imposed by the physical dimensions of the respective hardware. Additionally, a symmetric packaging of the conductive apertures and portions about a centerline of the printed circuit board allows for a simple design modification to allow for a two two-processor board to be manufactured from a similarly configured four-processor board.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: November 26, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Thomas Alex Crapisi, Jeffrey S. Conger, Stephen Cermak, III, Stephen A. Bowen, Rodney Ruesch, David Paul Gruber, Bonnie Kay Dobbs
  • Patent number: 4996454
    Abstract: High speed complex logic circuitry powered solely by clock signals. Such circuitry may be implemented in optical, electrical or other means, involving any medium or substrate as desired.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: February 26, 1991
    Assignee: Honeywell Inc.
    Inventors: Andrezj Peczalski, Julio C. Costa, Jeffrey S. Conger