Abstract: A system includes a display device configured to display frames of images, a memory coupled to the display device and configured to store image data representing a sequence of the frames, and a memory controller coupled to the memory. The memory controller is configured to split a frame in the sequence of frames into a slice count of frame slices according to an order of respective frame slice numbers, partition the memory into a number of buffer slices in an ordered sequence wherein the number of buffer slices is greater than or equal to the slice count, write each frame slice in the sequence of frames to a next free buffer slice in the ordered sequence of buffer slices, read each written frame slice to the display device to display the written frame slice with other displayed frame slices according to the order of the respective frame slice numbers, and return to a first buffer slice in the ordered sequence after writing a frame slice in a last buffer slice in the ordered sequence.

Abstract: A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.

Abstract: A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.

Abstract: The present application describes a system and method for selecting the best modulation sequence for an image (e.g., video, graphics or the like) on a frame-by-frame basis to optimize the system contrast ratio, brightness and black level based on a histogram of pixels in each frame. Embodiments described in this application include Pulse-Width Modulation (PWM) display systems such as DMD™. In an embodiment, the present invention uses the histogram of pixels in each frame of an image to select alternate color sequences for each frame of the image wherein the alternative color sequence includes reduced number of bits for color representations than the original color sequence.

Abstract: A formatter (13) for formatting data for use by a spatial light modulator (15) in an image display system (10). The formatter (13) converts data from pixel format to bit-plane format. The formatter (13) has a square array of memory cells (41), which are connected so that they can shift data either across the array from column to column (vertically) or down the array from row to row (horizontally). The loading of data to the array is toggled between vertical and horizontal loading (FIGS. 6A-6D). While the array is loaded vertically from one side, data is shifted out of the array at the other side. While the array is loaded horizontally from the top, data is shifted out at the bottom. Because of the orthogonal input versus output, the output data is arranged by bit-weight rather than by pixel.