Patents by Inventor Jeffrey S. Mailloux
Jeffrey S. Mailloux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7681005Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: GrantFiled: May 20, 1996Date of Patent: March 16, 2010Assignee: Micron Technology, Inc.Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
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Patent number: 7681006Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: GrantFiled: December 3, 1997Date of Patent: March 16, 2010Assignee: Micron Technology, Inc.Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
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Patent number: 7124256Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: GrantFiled: December 3, 1997Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
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Patent number: 7103742Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: GrantFiled: December 3, 1997Date of Patent: September 5, 2006Assignee: Micron Technology, Inc.Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
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Patent number: 6615325Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: GrantFiled: December 3, 1997Date of Patent: September 2, 2003Assignee: Micron Technology, Inc.Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
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Publication number: 20020133665Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: ApplicationFiled: December 3, 1997Publication date: September 19, 2002Inventors: JEFFREY S. MAILLOUX, KEVIN J. RYAN, TODD A. MERRITT, BRETT L. WILLIAMS
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Publication number: 20010044875Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: ApplicationFiled: December 3, 1997Publication date: November 22, 2001Inventors: JEFFREY S. MAILLOUX, KEVIN J. RYAN, TOBB A. MERRITT, BRETT L. WILLIAMS
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Patent number: 5907512Abstract: A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.Type: GrantFiled: October 20, 1993Date of Patent: May 25, 1999Assignee: Micron Technology, Inc.Inventors: Ward D. Parkinson, Jeffrey S. Mailloux, Eugene H. Cloud
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Patent number: 4891794Abstract: A three port memory device has two serial ports and a random access memory port. The random access memory port is addressed to a random access memory in a conventional manner, using RAS and CAS address signals. Data may also be supplied and retrieved through two serial ports to a pair of serial access memories for transfer between the serial ports and the random access memory. This configuration permits formatted data to be simultaneously assessed through the two serial ports, while the random access memory port is being accessed.Type: GrantFiled: June 20, 1988Date of Patent: January 2, 1990Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Jeffrey S. Mailloux, Eugene H. Cloud