Patents by Inventor Jeffrey S. Niew

Jeffrey S. Niew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6351011
    Abstract: A number of integrated circuit dies having on board protection against electrical overstress (EOS) transients are provided. Generally, the devices have an integrated circuit die with an outer periphery and a functional die area. A plurality of conductive input/output pads are formed on the integrated circuit die. Typically, a first conductive guard rail is disposed on the integrated circuit die and forms a gap between each one of the input/output pads. A voltage variable material is disposed in the gaps between the conductive guard rail and the input/output pads. Typically, a plurality of electrical leads are electrically connected to a respective one of the plurality of conductive input/output pads. At normal operating voltages, the voltage variable material is non-conductive. However, in response to an EOS transient, the voltage variable material switches to a low resistance state, providing a conductive path between the conductive guard rail and the input/output pads.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: February 26, 2002
    Assignee: Littlefuse, Inc.
    Inventors: Stephen J. Whitney, Edwin James Harris, IV, Jeffrey S. Niew, Michael J. Weber