Patents by Inventor Jeffrey S. Sather

Jeffrey S. Sather has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10921845
    Abstract: A real time clock and power management integrated circuit consists of a) an RTC block comprising an internal clock generator for generating a system clock signal that controls a device and b) a power management block. The power management block comprises primary and backup power source connections, a Feed Power Downconverter Component, a backup power source charger power booster/regulator component to increase or regulate voltage from the primary power source to a predetermined charger input voltage, a charge control logic component, a backup power source cut-off logic component, and a mode control logic component to enable operation of the charge control logic component and the battery cut-off logic component under predetermined conditions.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 16, 2021
    Assignee: CYMBET Corporation
    Inventors: Jeffrey S. Sather, Steve W. Tonkin, Jeffrey D. Mullin
  • Publication number: 20190101951
    Abstract: A real time clock and power management integrated circuit consists of a) an RTC block comprising an internal clock generator for generating a system clock signal that controls a device and b) a power management block. The power management block comprises primary and backup power source connections, a Feed Power Downconverter Component, a backup power source charger power booster/regulator component to increase or regulate voltage from the primary power source to a predetermined charger input voltage, a charge control logic component, a backup power source cut-off logic component, and a mode control logic component to enable operation of the charge control logic component and the battery cut-off logic component under predetermined conditions.
    Type: Application
    Filed: March 27, 2017
    Publication date: April 4, 2019
    Inventors: Jeffrey S. Sather, Steve W. Tonkin, Jeffrey D. Mullin
  • Publication number: 20190088979
    Abstract: Disclosed is a stacked array of a plurality of thin film batteries electrically connected in a staggered configuration, where the side edges of the array preferably generally conform to an interior surface of an electronic device or component thereof in order to save space. In an embodiment, a stacked array comprises at least one battery having a single surface in contact with a plurality of batteries. In another embodiment, a shaped array of a plurality of thin film batteries electrically are connected together, whereby a plurality of batteries are arranged in a single layer on a non-rectangular substrate adjacent to one another generally in the shape of the surface of the substrate. Additionally, a thin film battery is described having at least one via through the substrate and at least one other via through an insulation layer to provide electronic connection to the battery cell.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 21, 2019
    Inventors: Steven C. Grady, Jeffrey S. Sather, Blair A. Wilson
  • Patent number: 10079403
    Abstract: Disclosed is a stacked array of a plurality of thin film batteries electrically connected in a staggered configuration, where the side edges of the array preferably generally conform to an interior surface of an electronic device or component thereof in order to save space. In an embodiment, the stacked array comprises at least one battery having a single surface in contact with a plurality of batteries. In another embodiment, a shaped array of a plurality of thin film batteries electrically are connected together, whereby a plurality of batteries are arranged in a single layer on a non-rectangular substrate adjacent to one another generally in the shape of the surface of the substrate. Additionally, a thin film battery is described having at least one via through the substrate and at least one other via through an insulation layer to provide electronic connection to the battery cell.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: September 18, 2018
    Assignee: CYMBET CORPORATION
    Inventors: Steven C. Grady, Jeffrey S. Sather, Blair A. Wilson
  • Patent number: 9419463
    Abstract: A control system for charge and output control of a rechargeable thin film microbattery cell comprises a charge control logic component configured to control the level of charge of a thin film microbattery cell, a battery cut-off logic component to cease current draw on the thin battery thin film microbattery cell under predetermined conditions, a mode control logic component operably coupled to the charge control logic component and the battery cut-off logic component to enable operation of the charge control logic component and the battery cut-off logic component under predetermined conditions, and a Switch Capacitor DC-DC Downconverter Component for delivery of voltage external to the system configured to reduce battery output voltage potential by a factor of at least 2:1. Systems operably connected to a rechargeable thin film microbattery cell and powered devices comprising the system and the microbattery cell are also described.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 16, 2016
    Assignee: CYMBET CORPORATION
    Inventors: Jeffrey D. Mullin, Jeffrey S. Sather
  • Publication number: 20150200418
    Abstract: Disclosed is a stacked array of a plurality of thin film batteries electrically connected in a staggered configuration, where the side edges of the array preferably generally conform to an interior surface of an electronic device or component thereof in order to save space. In an embodiment, the stacked array comprises at least one battery having a single surface in contact with a plurality of batteries. In another embodiment, a shaped array of a plurality of thin film batteries electrically are connected together, whereby a plurality of batteries are arranged in a single layer on a non-rectangular substrate adjacent to one another generally in the shape of the surface of the substrate. Additionally, a thin film battery is described having at least one via through the substrate and at least one other via through an insulation layer to provide electronic connection to the battery cell.
    Type: Application
    Filed: November 26, 2014
    Publication date: July 16, 2015
    Inventors: Steven C. Grady, Jeffrey S. Sather, Blair A. Wilson
  • Publication number: 20140145680
    Abstract: A control system for charge and output control of a rechargeable thin film microbattery cell comprises a charge control logic component configured to control the level of charge of a thin film microbattery cell, a battery cut-off logic component to cease current draw on the thin battery thin film microbattery cell under predetermined conditions, a mode control logic component operably coupled to the charge control logic component and the battery cut-off logic component to enable operation of the charge control logic component and the battery cut-off logic component under predetermined conditions, and a Switch Capacitor DC-DC Downconverter Component for delivery of voltage external to the system configured to reduce battery output voltage potential by a factor of at least 2:1. Systems operably connected to a rechargeable thin film microbattery cell and powered devices comprising the system and the microbattery cell are also described.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Applicant: CYMBET Corporation
    Inventors: Jeffrey D. Mullin, Jeffrey S. Sather
  • Patent number: 8228023
    Abstract: A method and apparatus for a unitary battery and charging circuit. Also, having a power conversion system includes a variable charging source and an energy storage device. The power conversion circuit also includes a charging circuit coupled to the variable charging source and the energy storage device, the energy storage device being charged by the variable charging source. Further, the circuit includes an energy storage device isolation circuit configured to isolate the energy storage device from discharging when power from the variable charging source is below a predetermined threshold. Further still, the conversion circuit includes a restart circuit configured to restart the charging circuit by utilizing power from the energy storage device when charging power has dropped below a predetermined level.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: July 24, 2012
    Assignee: Cymbet Corporation
    Inventors: Jeffrey S. Sather, Roger L. Roisen, Jeffrey D. Mullin
  • Publication number: 20110183183
    Abstract: Disclosed is a stacked array of a plurality of thin film batteries that are electrically connected together. The stacked array is in a staggered configuration. The outermost points of side edges on one side of the stacked array preferably generally conform to an interior surface of an electronic device or component thereof in order to advantageously save space in the device. In an embodiment, the stacked array comprises at least one battery having a single surface in contact with a plurality of batteries. In another embodiment, a shaped array of a plurality of thin film batteries electrically connected together is provided, whereby a plurality of batteries are arranged in a single layer on a non-rectangular substrate adjacent to one another generally in the shape of the surface of the substrate. Additionally, a thin film battery is described wherein at least one via is provided through the substrate and at least one other via through an insulation layer to provide electronic connection to the battery cell.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 28, 2011
    Inventors: Steven C. Grady, Jeffrey S. Sather, Blair A. Wilson
  • Publication number: 20080203972
    Abstract: A method and apparatus for a unitary battery and charging circuit that includes a first substrate having integrated-circuit battery-charging circuitry thereon, and a cathode material, an anode material, and an electrolyte layer separating the cathode material from the anode material deposited on the substrate to form a battery, wherein the charging circuit is connected to the battery and encapsulated to form a surface-mount unitary package. Also, a power conversion system includes a variable charging source and an energy storage device. The power conversion circuit also includes a charging circuit coupled to the variable charging source and the energy storage device, the energy storage device being charged by the variable charging source. Further, the circuit includes an energy storage device isolation circuit configured to isolate the energy storage device from discharging when power from the variable charging source is below a predetermined threshold.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 28, 2008
    Inventors: Jeffrey S. Sather, Roger L. Roisen, Jeffrey D. Mullin
  • Patent number: 7166479
    Abstract: A monolithically formed ferromagnetic thin-film memory is disclosed that has local shielding on at least two sides of selected magnetic storage elements. The local shielding preferably extends along the back and side surfaces of a word line and/or digital lines of a conventional magnetic memory. In this configuration, the local shielding not only may help reduce externally generated EMI, internally generated cross-talk and other unwanted fields in the magnetic bit region, but may also help enhance the desired magnetic fields in the bit region.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Theodore Zhu, Jeffrey S. Sather
  • Patent number: 6872993
    Abstract: A monolithically formed ferromagnetic thin-film memory is disclosed that has local shielding on at least two sides of selected magnetic storage elements. The local shielding preferably extends along the back and side surfaces of a word line and/or digital lines of a conventional magnetic memory. In this configuration, the local shielding not only may help reduce externally generated EMI, internally generated cross-talk and other unwanted fields in the magnetic bit region, but may also help enhance the desired magnetic fields in the bit region.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: March 29, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Theodore Zhu, Jeffrey S. Sather
  • Patent number: 6175525
    Abstract: A non-volatile latch having a power supply terminal and a ground terminal is disclosed. The non-volatile latch includes a pair of cross-coupled inverter elements each having a power supply terminal and a ground terminal. Magneto-resistive elements are interposed between the power supply terminals of both cross-coupled inverter elements and the power supply terminal of the non-volatile latch. In addition, magneto-resistive elements are interposed between the ground terminals of both cross-coupled inverter elements and the ground terminal of the non-volatile latch. By including magneto-resistive elements in each supply line, the effects of transistor parameter variation can be minimized.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: January 16, 2001
    Assignee: Honeywell Inc.
    Inventors: David E. Fulkerson, Yong Lu, Allen T. Hurst, Jr., Jeffrey S. Sather, Jason B. Gadbois
  • Patent number: 6048739
    Abstract: A high density magnetic memory device and method of manufacture therefor, wherein the magnetic bit region is provided after selected higher temperature processing steps are performed. Illustrative higher temperature processing steps include those that are performed above for example 400.degree. C., any may include contact and via plug processing. The present invention may allow, for example, contact and via plug processing to be used to form magnetic RAM devices. As indicated above, contact and/or via plug processing typically allows the size of the contacts and vias to be reduced, and the packing density of the resulting memory device to be increased.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: April 11, 2000
    Assignee: Honeywell Inc.
    Inventors: Allan T. Hurst, Jeffrey S. Sather, William F. Witcraft, Cheisan J. Yue