Patents by Inventor Jeffrey S. Wilder

Jeffrey S. Wilder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9977482
    Abstract: An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Ian M. Steiner, Krishnakanth V. Sistla, Matthew M. Bace, Vivek Garg, Martin T. Rowland, Jeffrey S. Wilder
  • Publication number: 20140281270
    Abstract: Methods and apparatus relating to directory based coherency to improve input/output write bandwidth in scalable systems are described. In one embodiment, a first agent receives a request to write data from a second agent via a link and logic causes the first agent to write the directory state to an Input/Output Directory Cache (IODC) of the first agent. Additionally, the logic causes the second agent to send data from a modified state to an exclusive state using write back to the first agent, while allowing the data to remain cached exclusively in the second agent and also enabling the deallocation of the IODC entry in the first agent. Other embodiments are also disclosed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Henk G. Neefs, Ganesh Kumar, Vedaraman Geetha, Jeffrey D. Chamberlain, Sailesh Kottapalli, Jeffrey S. Wilder
  • Publication number: 20140129858
    Abstract: An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
    Type: Application
    Filed: December 21, 2011
    Publication date: May 8, 2014
    Inventors: Ankush Varma, Ian M. Steiner, Krishnakanth V. Sistla, Matthew M. Bace, Vivek Garg, Martin T. Rowland, Jeffrey S. Wilder