Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.

Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.

Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.

Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.

Abstract: An integrated circuit capable of monitoring aging effects on an integrated circuit device is disclosed. The integrated circuit includes a control circuit that obtains a clock signal at different frequencies. A sense circuit may receive the clock signal. First and second control signals may be asserted on the integrated circuit with the control circuit. The first control signal may activate a stress mode, and the second control signal may activate a measurement mode. During stress mode, the sense circuit may receive the clock signal. Any changes in predetermined electrical parameters of one or more transistors in the sense circuit may be monitored and measured during the measurement mode. Aging compensation may be performed when aging effect is detected on the sense circuit.

Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract: An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Abstract: Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.

Abstract: Illustratively, a finFET comprises at least one fin, and typically several fins, with a trapping region in or on a substrate at the base of each fin to trap ions produced by radiation incident on the substrate. In one embodiment, the trapping region is an implanted region having a conductivity type opposite that of the substrate. In another, the trapping region is a defect region. In another, the trapping region is an epitaxial region grown on the substrate. The finFET is formed by forming the fin or fins and then forming the trapping region at the base of the fin. Illustratively, the trapping region is formed by implanting in the substrate ions having a conductivity type opposite that of the substrate or by creating defects in the substrate or by epitaxially growing a region or regions having an opposite conductivity type to that of the substrate.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: An integrated circuit system, and a method of manufacture thereof, includes: an integrated circuit substrate; and a discretized tunable precision resistor having a total resistance including: a resistor body over the integrated circuit substrate, interconnects directly on the resistor body, metal taps directly on the interconnects and at opposing sides of the resistor body, and conductive metal strips over the interconnects, wherein the total resistance is a function of an active resistor length of the resistor body between a pair of the metal taps in contact with two of the conductive metal strips.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.

Abstract: An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.

Abstract: A capacitor structure having a complete terminal shield is provided. The capacitor structure may include a first conductive segment with a first set of conductive fingers and a second segment structure with a second set of conductive fingers. The second set of conductive fingers may be spatially interleaved with the first set of conductive fingers in the first conductive structure. The first conductive segment may receive a first voltage, whereas the second conductive segment may receive a second voltage that is different than the first voltage. The capacitor structure further includes a conductive shielding structure that is connected to the first conductive segment. The conductive shielding structure may laterally surround the second conductive segment from at least three sides. An additional conductive shielding structure that connects to the first and second conductive segments is formed directly above the first and second conductive segments.

Abstract: An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.