Abstract: A synchronization backbone for use in a computer system having a system board containing at least one central processing unit for processing digital data, a memory coupled to the system board for storing the digital data, a plurality of subsystems, and a bus structure for transmitting electrical signals between the system board, the memory, and the plurality of subsystems. The synchronization backbone provides the infrastructure that enables professional quality synchronization between the various subsystems. A clock generator is used to generate a system clock that is transmitted to each of the subsystems. The sample rate of a designated subsystem is used as a digital synchronization signal. The selected digital synchronization signal is then transmitted to each of the other subsystems. A synchronization circuit adjusts the sample rates associated with the other subsystems according to the digital synchronization signal and the system clock.