Abstract: Techniques are disclosed relating to thread preemption in the context of memory-backed registers. In some embodiments, a memory hierarchy includes one or more cache levels and one or more memory circuits. Execution circuitry may operate on operands in architectural registers to execute instructions of threads, where data for the architectural registers is stored and backed by the memory hierarchy. Control circuitry may, in response to a context switch indication for a given thread: flush and invalidate a set of architectural register data from a first cache level and store memory page information (e.g., a page catalog base address) associated with the set of architectural register data.

Abstract: Genes and gene expression profiles useful for predicting outcome, risk classification, cytogenetics and/or etiology in pediatric acute lymphoblastic leukemia (ALL). OPAL1 is a novel gene associated with outcome and, along with other newly identified genes, represent a novel therapeutic targets.