Patents by Inventor Jeffrey W. Thomas

Jeffrey W. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080254617
    Abstract: A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer (30), a titanium nitride barrier layer (40), and a tungsten seed layer (50) in a contact opening (24). The contact hole (24) is then filled up from a bottom surface of the contact opening by electroplating a copper layer (60) so that no voids are formed in the contact opening (24). Any excess metal is removed with a CMP process to form the contact plugs (70), where the CMP process may also used to thin or remove one or more of the contact/seed/barrier layers (30, 40, 50).
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: Olubunmi O. Adetutu, Elsie D. Banks, Jeffrey W. Thomas
  • Patent number: 7435646
    Abstract: A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: October 14, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jeffrey W. Thomas, Olubunmi O. Adetutu