Patents by Inventor Jeffry V. Herring

Jeffry V. Herring has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • State machine bus controller providing function and timing parameters to satisfy requirements of asynchronous bus and more than one type of device on the bus
    Patent number: 5944799
    Abstract: A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: August 31, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Charles H. Smoot, III, Ronald J. Larson, Jeffry V. Herring, Jean-Pierre Dupont, Richard Matysiak
  • State machine bus controller
    Patent number: 5640585
    Abstract: A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 17, 1997
    Assignee: AST Research, Inc.
    Inventors: Charles H. Smoot, III, Ronald J. Larson, Jeffry V. Herring, Jean-Pierre Dupont, Richard Matysiak
  • System for matching data recovery time between different devices by extending a cycle upon detecting end of cycle
    Patent number: 5220659
    Abstract: A controller for interfacing bus-coupled peripheral devices with a microcomputer is described. The controller provides generalized compensation for variations in peripheral device access recovery time and for differences in access recovery times among peripheral devices, central processing units and input/output buses.
    Type: Grant
    Filed: September 18, 1989
    Date of Patent: June 15, 1993
    Assignee: Micral, Inc.
    Inventors: Ronald J. Larson, Jeffry V. Herring
  • Memory controller with synchronous processor bus and asynchronous I/O bus interfaces
    Patent number: 5187779
    Abstract: An asynchronous memory control Unit for asynchronously controlling access to and from system memory of a microcomputer system in response to control signals from conventional and state-of-the-art microcomputer I/O buses is described. The asynchronous memory control unit of the present invention operates cooperatively with a synchronous memory control unit which provides access to and from system memory in response to command signals from a microprocessor. Whenever the microprocessor controls the bus, the synchronous memory control unit is enabled; whenever the microprocessor is not controlled of the bus at main IO bus, the asynchronous control unit is enabled.
    Type: Grant
    Filed: August 11, 1989
    Date of Patent: February 16, 1993
    Assignee: Micral, Inc.
    Inventors: Joseph M. Jeddeloh, Ronald J. Larson, Jeffry V. Herring