Abstract: The present invention enables interface conversion verification with a single chip and improves problem isolation. Exemplary embodiments of the present invention can provide this by modifying the input data pattern (e.g., creating a 40G, or pseudo OC-768, frame by multiplexing four OC-192 frames, two bytes at a time) to provide per port demultiplexing of data streams at the output of the interface converter.

Abstract: The present invention enables interface conversion verification with a single chip and improves problem isolation. Exemplary embodiments of the present invention can provide this by modifying the input data pattern (e.g., creating a 40G, or pseudo OC-768, frame by multiplexing four OC-192 frames, two bytes at a time) to provide per port demultiplexing of data streams at the output of the interface converter.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

Abstract: A battery charge controller (50) is provided which includes a PWM switch controller (36) that is operable to control a switching regulator to supply current to a battery (10) in either a current regulation mode or a voltage regulation mode. A charge control (40) is operable to control the charging operation such that multiple modes of operation are selectable by an external programmable pin. The three modes provided are: a constant voltage mode, a dual-current mode and a pulse-current mode. The constant voltage mode provides for a conditioning state followed by a bulk charging state followed by a maintenance state. In the bulk charging state, current regulation is provided at a maximum current until a charged condition occurs, at which time the charger is placed in a voltage regulation mode.

Abstract: A battery charge controller (50) is provided which includes a PWM switch controller (36) that is operable to control a switching regulator to supply current to a battery (10) in either a current regulation mode or a voltage regulation mode. A charge control (40) is operable to control the charging operation such that multiple modes of operation are selectable by an external programmable pin. The three modes provided are: a constant voltage mode, a dual-current mode and a pulse-current mode. The constant voltage mode provides for a conditioning state followed by a bulk charging state followed by a maintenance state. In the bulk charging state, current regulation is provided at a maximum current until a charged condition occurs, at which time the charger is placed in a voltage regulation mode.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.