Patents by Inventor Jei-Feng Hwang
Jei-Feng Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6569730Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: March 6, 2002Date of Patent: May 27, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Publication number: 20020105054Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: ApplicationFiled: March 6, 2002Publication date: August 8, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6423590Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: May 2, 2001Date of Patent: July 23, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6396126Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: August 17, 2001Date of Patent: May 28, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jyh-Min Jiang, Jei-Feng Hwang
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Patent number: 6291304Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: September 15, 1999Date of Patent: September 18, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsaz, Ruey-Hsin Liu, Jyh-Min Jiang, Jei-Feng Hwang
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Publication number: 20010017379Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: ApplicationFiled: May 2, 2001Publication date: August 30, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6245609Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: September 27, 1999Date of Patent: June 12, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6242313Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates.Type: GrantFiled: September 3, 1999Date of Patent: June 5, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jei-Feng Hwang, Jun-Lin Tsai, Ruey-Hsin Liou, Jyh-Min Jiang
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Patent number: 6162695Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and located between a base and collector region. The use of the field ring results in an increase in collector-emitter breakdown voltage, as a result of the reduction in local dopant concentration in the N well region. This phenomena, the reduction the local dopant concentration in the N well region, in the vicinity of the field ring region, allows a higher N well dopant concentration to be used, resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated without the field ring regions, and thus with a lower N well dopant concentration.Type: GrantFiled: August 18, 1999Date of Patent: December 19, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jei-Feng Hwang, Jun-Lin Tsai, Ruey-Hsin Liou, Kuo-Chio Liu