Patents by Inventor Jein-Chen Young
Jein-Chen Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7408212Abstract: An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., Pr0.7Ca0.3MnO3). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.Type: GrantFiled: February 11, 2004Date of Patent: August 5, 2008Assignee: Winbond Electronics CorporationInventors: Harry S. Luan, Jein-Chen Young, Arthur Wang, Kai-Cheng Chou, Kenlin Huang
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Patent number: 7186658Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.Type: GrantFiled: May 24, 2004Date of Patent: March 6, 2007Assignee: Winbond Electronics CorporationInventors: Kenlin Huang, Kaicheng Chou, Harry Luan, Jein-Chen Young, Arthur Wang
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Patent number: 6693830Abstract: An EEPROM cell includes a sense transistor and a select transistor, each having a first active region (110, 114) formed in a substrate, and sharing a second active region (112). The EEPROM cell may also include a floating gate (125) having a first portion (FG2) forming a gate region for said sense transistor, and a second portion (FG1) overlying the second active region and forming a program junction with said second active region. The first portion of said floating gate has a concentration of an impurity greater than a concentration of said impurity in the second portion of the floating gate.Type: GrantFiled: October 22, 2001Date of Patent: February 17, 2004Assignee: Lattice Semiconductor Corp.Inventors: Yongzhong Hu, Jein-Chen Young
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Patent number: 6627947Abstract: A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.Type: GrantFiled: August 22, 2000Date of Patent: September 30, 2003Assignee: Lattice Semiconductor CorporationInventors: Yongzhong Hu, Jein Chen Young, Stewart Logie
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Patent number: 6525970Abstract: A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about −9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.Type: GrantFiled: October 12, 2001Date of Patent: February 25, 2003Assignee: Hyundai Electronics AmericaInventors: Arthur Wang, Jein-Chen Young, Ming Kwan
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Publication number: 20020048192Abstract: A structure for a flash memory cell is described in which a triple well is formed with the memory cell residing in a P-well, which in turn is deposed in an N-well in a P-type substrate. The structure provides the ability to operate such memories with considerably lower operating potentials than prior art devices. A process for fabricating the flash memory cell is also described.Type: ApplicationFiled: October 12, 2001Publication date: April 25, 2002Inventors: Hsingya Arthur Wang, Jein-Chen Young, Ming-Sang Kwan
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Patent number: 6366499Abstract: A method of programming an electrically programmable memory cell which cell includes a transistor formed in a semiconductor substrate of first conductivity type having a surface a first well region of second conductivity type is disposed in the substrate adjacent the surface thereof. A second well region of first conductivity type is disposed in the first well region adjacent the surface. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes raising the control gate to a first selected potential no greater than 9.0 volts, raising the drain to a potential to no more than 5.0 volts, coupling the source region to ground potential, coupling the first well region of second conductivity type to ground potential, and placing the second well region at a potential below ground potential.Type: GrantFiled: October 10, 2000Date of Patent: April 2, 2002Assignee: Hyundai Electronics AmericaInventors: Arthur Arthur Wang, Jein-Chen Young, Ming Kwan
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Patent number: 6347054Abstract: A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential no more negative than 6.5 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential no more positive than 8.0 volts.Type: GrantFiled: February 1, 2000Date of Patent: February 12, 2002Assignee: Hyundai Electronics AmericaInventors: Arthur Arthur Wang, Jein-Chen Young, Ming-Sang Kwan
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Patent number: 6330190Abstract: A semiconductor structure for a flash memory has memory cells which are formed in a first conductivity type well, which in turn is formed within an opposite conductivity type well. The opposite conductivity type well is formed in the substrate. Additional regions within each of the first and opposite conductivity type wells are used to provide electrical connections to the corresponding well. This structure is particularly advantageous because it provides the ability to operate the flash memory with considerably lower operating potentials than prior art flash memories.Type: GrantFiled: May 27, 1997Date of Patent: December 11, 2001Assignee: Hyundai Electronics AmericaInventors: Arthur Wang, Jein-Chen Young, Ming Kwan
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Patent number: 6043123Abstract: A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.Type: GrantFiled: May 27, 1997Date of Patent: March 28, 2000Assignee: Hyundai Electronics America, Inc.Inventors: Hsingya Arthur Wang, Jein-Chen Young, Ming-Sang Kwan
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Patent number: 5920506Abstract: Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.Type: GrantFiled: September 26, 1997Date of Patent: July 6, 1999Assignee: Hyundai Electronics America, Inc.Inventors: Hsingya Arthur Wang, Haike Dong, Jein-Chen Young, Yuan Tang, Aaron Yip, Kenneth Miu
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Patent number: 5899726Abstract: After providing a patterned nitride layer over a patterned layer of oxide in turn disposed on a silicon substrate, a covering layer of oxide or polysilicon is deposited over the resulting structure to contact the substrate to hold the patterned nitride layer portions in position as field oxide is grown. In addition, field oxide growth rate slows at the edges of the nitride layer portions, allowing additional time for field oxide to flow as it is grown, relieving lifting force on the nitride layer portions, and providing an increase in silicon active area between field oxide regions.Type: GrantFiled: July 14, 1997Date of Patent: May 4, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Hsingya Arthur Wang, Mark T. Ramsbey, Jein-Chen Young
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Patent number: 5866467Abstract: A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropically etched to form spacers on the side of the nitride layer portions, which are also in contact with the silicon substrate, the etching continuing into the silicon substrate. Field oxidation is then undertaken, with the polysilicon spacers being oxidized, as is a portion of the silicon substrate, the spacers causing initial oxidation during field oxide growth to be removed from the sides of the nitride layer portions, so that encroachment of the oxide under the nitride layer portions is avoided.Type: GrantFiled: July 1, 1997Date of Patent: February 2, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Hsingya Arthur Wang, Jein-Chen Young, Nicholas H. Tripsas
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Patent number: 5818082Abstract: An E.sup.2 PROM device includes a semiconductor body having source and drain regions and a channel region, with a gate oxide over the channel region and a floating gate over the gate oxide. An oxide isolation region contains a doped polysilicon erase gate, so that erasing of the device takes place by electron flow from the floating gate to the erase gate through a thin oxide portion of the oxide isolation region, at a position spaced from the gate oxide. The inclusion of the erase gate in the oxide isolation region results in smaller overall device size than previously achieved.Type: GrantFiled: March 4, 1996Date of Patent: October 6, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Hsingya Arthur Wang, Jein-Chen Young, Darlene Hamilton
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Patent number: 5278438Abstract: A nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.Type: GrantFiled: December 19, 1991Date of Patent: January 11, 1994Assignee: North American Philips CorporationInventors: Manjin J. Kim, Jein-Chen Young