Patents by Inventor Jen-Che Tsai
Jen-Che Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9876517Abstract: A radio frequency (RF) receiver includes a digital tuning engine; and I-path and Q-path analog filters, tuned by the digital tuning engine. The digital tuning engine gets an I/Q imbalance difference, and the digital tuning engines tunes the I-path analog filter and/or the Q-path analog filter based on the I/O imbalance difference.Type: GrantFiled: June 30, 2015Date of Patent: January 23, 2018Assignee: MEDIATEK INC.Inventors: Sheng-Hong Yan, Sheng-Hao Chen, Paul Cheng Po Liang, Jen-Che Tsai
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Patent number: 9385740Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.Type: GrantFiled: October 22, 2015Date of Patent: July 5, 2016Assignee: MEDIATEK INC.Inventors: Chi Yun Wang, Jen-Che Tsai, Shu-Wei Chu
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Publication number: 20160134300Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.Type: ApplicationFiled: October 22, 2015Publication date: May 12, 2016Inventors: Chi Yun Wang, Jen-Che Tsai, SHU-WEI CHU
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Publication number: 20150303957Abstract: A radio frequency (RF) receiver includes a digital tuning engine; and I-path and Q-path analog filters, tuned by the digital tuning engine. The digital tuning engine gets an I/Q imbalance difference, and the digital tuning engines tunes the I-path analog filter and/or the Q-path analog filter based on the I/Q imbalance difference.Type: ApplicationFiled: June 30, 2015Publication date: October 22, 2015Inventors: Sheng-Hong Yan, Sheng-Hao Chen, Paul Cheng Po Liang, Jen-Che Tsai
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Patent number: 9100078Abstract: A radio frequency (RF) receiver includes a digital tuning engine; I-path and Q-path analog filters, tuned by the digital tuning engine; and a digital compensation circuit. The digital tuning engine executes a RC (resistor-capacitor) time constant calibration to adjust respective cut-off frequencies of the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter mismatch calibration to match the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter residual mismatch calibration to match an I-path response from the I-path analog filter to the digital compensation circuit and a Q-path response from the Q-path analog filter to the digital compensation circuit.Type: GrantFiled: March 13, 2013Date of Patent: August 4, 2015Assignee: MEDIATEK INC.Inventors: Sheng-Hong Yan, Sheng-Hao Chen, Paul Cheng Po Liang, Jen-Che Tsai
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Patent number: 9094034Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.Type: GrantFiled: September 10, 2014Date of Patent: July 28, 2015Assignee: MEDIATEK INC.Inventors: Sheng-Hao Chen, Yen-Chuan Huang, Min-Hua Wu, Chun-Hao Liao, Hung-Pin Ma, Tzu-Hao Yu, Jen-Che Tsai
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Publication number: 20150123830Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.Type: ApplicationFiled: September 10, 2014Publication date: May 7, 2015Inventors: Sheng-Hao Chen, Yen-Chuan Huang, Min-Hua Wu, Chun-Hao Liao, Hung-Pin Ma, Tzu-Hao Yu, Jen-Che Tsai
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Patent number: 8669896Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.Type: GrantFiled: June 11, 2012Date of Patent: March 11, 2014Assignee: Mediatek Inc.Inventors: Jen-Che Tsai, Chao-Hsin Lu
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Patent number: 8629793Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal.Type: GrantFiled: August 3, 2011Date of Patent: January 14, 2014Assignee: Mediatek Inc.Inventor: Jen-Che Tsai
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Publication number: 20130266102Abstract: A radio frequency (RF) receiver includes a digital tuning engine; I-path and Q-path analog filters, tuned by the digital tuning engine; and a digital compensation circuit. The digital tuning engine executes a RC (resistor-capacitor) time constant calibration to adjust respective cut-off frequencies of the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter mismatch calibration to match the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter residual mismatch calibration to match an I-path response from the I-path analog filter to the digital compensation circuit and a Q-path response from the Q-path analog filter to the digital compensation circuit.Type: ApplicationFiled: March 13, 2013Publication date: October 10, 2013Applicant: MEDIATEK Inc.Inventors: Sheng-Hong Yan, Sheng-Hao Chen, Cheng-Po Liang, Jen-Che Tsai
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Patent number: 8462960Abstract: A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced.Type: GrantFiled: May 28, 2008Date of Patent: June 11, 2013Assignee: Mediatek Inc.Inventors: Sheng-Jui Huang, Yung-Yu Lin, Jen-Che Tsai, Tzueng-Yau Lin, Yau-Wai Wong, Chih-Horng Weng, Chi-Hui Wang
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Publication number: 20130099953Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.Type: ApplicationFiled: June 11, 2012Publication date: April 25, 2013Inventors: Jen-Che Tsai, Chao-Hsin Lu
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Patent number: 8218793Abstract: An apparatus and a muting circuit. The apparatus comprises an amplifier, a mute circuit, a pull-down circuit, and a power detection circuit. The amplifier receives a power supply voltage and a common mode voltage, and amplifies an audio input signal to generate an audio output signal. The mute circuit, coupled to the amplifier, conducts the audio output signal to about ground level upon receiving a mute signal. The pull-down circuit, coupled to the amplifier, pulls the common mode voltage to about ground level upon receiving a pull-down signal. The power detection circuit, coupled to the mute circuit and the pull-down circuit, detects power-up or power-down of the power supply voltage, and generates the mute signal and a pull-down signal according to the power-up or power-down operation.Type: GrantFiled: December 4, 2007Date of Patent: July 10, 2012Assignee: Mediatek Inc.Inventors: Jen-Che Tsai, Yau-Wai Wong
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Patent number: 8171335Abstract: A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.Type: GrantFiled: June 8, 2009Date of Patent: May 1, 2012Assignee: Mediatek Inc.Inventor: Jen-Che Tsai
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Publication number: 20110285562Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal.Type: ApplicationFiled: August 3, 2011Publication date: November 24, 2011Inventor: Jen-Che Tsai
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Publication number: 20110221618Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) with a compact structure comprises a loop filter, a summing circuit, a quantizer, and a current Digital to Analog Converter (DAC). The loop filter is utilized for receiving and noise-shaping an analog input signal, and accordingly outputting a positive and a negative loop voltages. The summing circuit comprises a positive and a negative summing resistors. The summing resistors are utilized for transforming a positive and negative feedback currents to be a positive and a negative feedback voltages, and summing the loop voltages and the feedback voltages so as to generate a positive and a negative summing voltages, respectively. The quantizer is utilized for outputting a digital output signal according to a difference between the positive and the negative summing voltages. The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal.Type: ApplicationFiled: March 14, 2010Publication date: September 15, 2011Inventor: Jen-Che Tsai
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Patent number: 8018365Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) with a compact structure comprises a loop filter, a summing circuit, a quantizer, and a current Digital to Analog Converter (DAC). The loop filter is utilized for receiving and noise-shaping an analog input signal, and accordingly outputting a positive and a negative loop voltages. The summing circuit comprises a positive and a negative summing resistors. The summing resistors are utilized for transforming a positive and negative feedback currents to be a positive and a negative feedback voltages, and summing the loop voltages and the feedback voltages so as to generate a positive and a negative summing voltages, respectively. The quantizer is utilized for outputting a digital output signal according to a difference between the positive and the negative summing voltages. The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal.Type: GrantFiled: March 14, 2010Date of Patent: September 13, 2011Assignee: Mediatek Inc.Inventor: Jen-Che Tsai
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Publication number: 20100066422Abstract: A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.Type: ApplicationFiled: June 8, 2009Publication date: March 18, 2010Inventor: Jen-Che Tsai
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Patent number: 7663525Abstract: A digital to analog converter including a first capacitor, a second capacitor, an operational amplifier, and a switch is disclosed. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier comprises an input and an output. The switch parallels the first and the second capacitors with the operational amplifier at the input and output according to a digital signal during a second period.Type: GrantFiled: July 30, 2007Date of Patent: February 16, 2010Assignee: Mediatek Inc.Inventor: Jen-Che Tsai
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Publication number: 20090296950Abstract: A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced.Type: ApplicationFiled: May 28, 2008Publication date: December 3, 2009Inventors: Sheng-Jui Huang, Yung-Yu Lin, Jen-Che Tsai, Tzueng-Yau Lin, Yau-Wai Wong, Chih-Horng Weng, Chi-Hui Wang