Patents by Inventor Jen-Chieh Yeh
Jen-Chieh Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145357Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Lin YEH, Jen-Chieh KAO
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Publication number: 20240126327Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
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Patent number: 9472249Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: GrantFiled: August 18, 2015Date of Patent: October 18, 2016Assignee: INTEL CORPORATIONInventors: Andre Schaefer, Jen-Chieh Yeh, Pei-Wen Luo
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Publication number: 20150357011Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Applicant: INTEL CORPORATIONInventors: ANDRE SCHAEFER, JEN-CHIEH YEH, PEI-WEN LUO
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Patent number: 9135982Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: GrantFiled: December 18, 2013Date of Patent: September 15, 2015Assignee: INTEL CORPORATIONInventors: Andre Schaefer, Jen-Chieh Yeh, Pei-Wen Luo
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Publication number: 20150170729Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: ANDRE SCHAEFER, JEN-CHIEH YEH, PEI-WEN LUO
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Patent number: 8756544Abstract: A method for inserting characteristic extractor is provided. The method includes parsing a transaction level model (TLM) of an electronic device of a target system to find out at least one target point of an operation status of the electronic device; and inserting at least one characteristic extractor into the at least one target point.Type: GrantFiled: March 26, 2013Date of Patent: June 17, 2014Assignee: Industrial Technology Research InstituteInventors: Yi-Siou Chen, Tung-Hua Yeh, Jen-Chieh Yeh, Wen-Tsan Hsieh
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Patent number: 8510694Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.Type: GrantFiled: March 7, 2011Date of Patent: August 13, 2013Assignee: Industrial Technology Research InstituteInventors: Wen-Tsan Hsieh, Jen-Chieh Yeh, Hong-Jie Huang, I-Yao Chuang
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Publication number: 20130054854Abstract: The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.Type: ApplicationFiled: February 16, 2012Publication date: February 28, 2013Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Hong-Jie Huang, Jen-Chieh Yeh, Ren-Song Tsay
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Publication number: 20120144216Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.Type: ApplicationFiled: March 7, 2011Publication date: June 7, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen-Tsan Hsieh, Jen-Chieh Yeh, Hong-Jie Huang, I-Yao Chuang
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Publication number: 20120089385Abstract: A memory modeling method is provided. According to the memory modeling method, a memory model is provided. The memory model includes an array unit, and the array unit includes an array declaration module and a calculation module. A virtual array is defined in a storage device by the array declaration module. The virtual array is configured to simulate a real memory. Further, according to the memory modeling method, an access instruction is received, and an access operation corresponding to the access instruction is performed to the virtual array, wherein the access operation is performed with a transaction level modeling method. Then, an access time or a delay time of the access operation according to the access instruction is estimated by the calculation module.Type: ApplicationFiled: March 25, 2011Publication date: April 12, 2012Inventors: Che-Mao HSU, Jen-Chieh YEH, Hsun-Lun HUANG
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Publication number: 20060156187Abstract: An apparatus for multiple polynomial-based random number generation includes an LUT device having a plurality of polynomials established therein, a signal selection unit coupled to the LUT device and operable so as to generate a select signal that is inputted to the LUT device to thereby select at least one of the polynomials established in the LUT device, and an LFSR device coupled to the LUT device and operable so as to perform LFSR operations based on the at least one of the polynomials selected from the LUT device. A method for multiple polynomial-based random number generation includes: a) establishing the polynomials in the LUT device, b) generating the select signal to select at least one of the polynomials, and c) enabling the LFSR device to perform the corresponding LFSR operations.Type: ApplicationFiled: October 13, 2005Publication date: July 13, 2006Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Cheng-Wen Wu, Jen-Chieh Yeh, Hung-hsun Ou
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Patent number: 7065689Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in ?45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.Type: GrantFiled: June 24, 2003Date of Patent: June 20, 2006Assignees: Spirox Corporation/National, Tsing Hua UniversityInventors: Sau-Kwo Chiu, Jen-Chieh Yeh, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
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Publication number: 20050140294Abstract: A cold cathode fluorescent lamp. The cold cathode fluorescent lamp includes a transparent tube, at least one absorptive structure and at least one absorptive layer. The transparent tube is filled with a gas including a material capable of arousing light by means, of an electric potential. The absorptive structure is disposed on one end of the transparent tube and includes a supporting mechanism having at least one opening. The absorptive layer is formed in the opening and is not filled with the opening.Type: ApplicationFiled: December 27, 2004Publication date: June 30, 2005Inventors: Ruey-Feng Jean, Jen-Chieh Yeh, Kuang-Lung Tsai, Shih-Hsien Lin
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Publication number: 20040015756Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in −45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.Type: ApplicationFiled: June 24, 2003Publication date: January 22, 2004Inventors: Sau-Kwo Chiu, Jen-Chieh Yeh, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu