Patents by Inventor Jen-Hong Huang

Jen-Hong Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179875
    Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Jung CHEN, Yu-Nien HUANG, Sin-Hong LIEN, Jen-Mao CHEN
  • Patent number: 11937405
    Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: March 19, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Yu Nien Huang, Sin-Hong Lien, Jen-Mao Chen
  • Patent number: 7858147
    Abstract: A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 28, 2010
    Assignee: National Tsing Hua University
    Inventors: Yu-Tsung Wu, Jen-Hong Huang, Chung-Min Tsai, Huan-Chieh Su, Tri-Rung Yew
  • Publication number: 20090197113
    Abstract: A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.
    Type: Application
    Filed: August 20, 2008
    Publication date: August 6, 2009
    Applicant: National Tsing Hua University
    Inventors: Yu-Tsung Wu, Jen-Hong Huang, Chung-Min Tsai, Huan-Chieh Su, Tri-Rung Yew
  • Patent number: 7528045
    Abstract: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: May 5, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chiang Wu, Shih-Fang Tzou, Shih-Chieh Hsu, Jen-Hong Huang
  • Publication number: 20090072325
    Abstract: A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar.
    Type: Application
    Filed: November 23, 2008
    Publication date: March 19, 2009
    Inventors: Chih-Chiang Wu, Shih-Fang Tzou, Shih-Chieh Hsu, Jen-Hong Huang
  • Publication number: 20080179626
    Abstract: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Inventors: Chih-Chiang Wu, Shih-Fang Tzou, Shih-Chieh Hsu, Jen-Hong Huang
  • Publication number: 20070087542
    Abstract: At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the first dielectric layer is removed to form a notch between the gate electrode and the spacer, the notch having an aspect ratio greater than 1. A self-aligned silicide process is performed to form a silicide on exposed surfaces of the gate electrode and the first dielectric layer underneath the notch.
    Type: Application
    Filed: December 6, 2006
    Publication date: April 19, 2007
    Inventors: Jen-Hong Huang, Nien-Chung Li, Yi-Chung Sheng, Chun-Chia Chen
  • Publication number: 20070042584
    Abstract: At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the first dielectric layer is removed to form a notch between the gate electrode and the spacer, the notch having an aspect ratio greater than 1. A self-aligned silicide process is performed to form a silicide on exposed surfaces of the gate electrode and the first dielectric layer underneath the notch.
    Type: Application
    Filed: August 16, 2005
    Publication date: February 22, 2007
    Inventors: Jen-Hong Huang, Nien-Chung Li, Yi-Chung Sheng, Chun-Chia Chen