Abstract: A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating gate oxide layer including respective lateral tip portions, whereby the forward tunneling voltage of the FLASH memory is improved. In one embodiment, the respective tip portions have an average width of greater than or equal to about 250 ?.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications.

Abstract: A method for forming a self-aligned contact in a IC device is disclosed. In the method, a gate oxide layer, a polysilicon layer and a metal silicide layer are first deposited and patterned on a substrate. A first silicon dioxide layer is then deposited on the polysilicon layer followed by the deposition of a silicon nitride cap layer on the first silicon dioxide layer. A second silicon oxide layer is deposited on the silicon nitride cap layer and the stack is patterned forming an oxide-nitride-oxide hard mask. The substrate is then wet etched by an etchant that has low selectivity toward silicon oxide and high selectivity to nitride and silicide, thus forming a toroidal-shaped recess between the silicon nitride layer. A second silicon nitride layer is deposited over the whole substrate. A dielectric layer is formed over the whole substrate.

Abstract: A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

Abstract: A method of preventing photoresist residue on metal lines is disclosed herein. A strip recipe with a preheat step has been developed for use with the Applied Materials Mxp Centura. The preheat step is performed before the strip step. The preheat step can rapidly shorten the temperature balance time between the wafer and the strip chamber and make the photoresist flow to increase photoresist surface area. Therefore, the strip photoresist rate will be improved by higher wafer temperature in the first few strip cycles.