Abstract: A circuit and method are given, to realize a high efficiency voltage multiplier for integrated circuits generating an internal and flexible positive or negative high voltage on-chip supply voltage from low external positive or negative supply voltages or ground. Applying multi-phase control signals to voltage boost internal nodes allows for eliminating threshold voltage drop losses and thus improves the voltage pumping gain compared to circuits with diode-configured FETs of prior art. Making use of voltage signals from antecedent stages in order to bias the bulk of MOS transistors fabricated in triple-well technology enables relaxing of the gate oxide stress within high order stage MOS transistors. Such a method, called leap-frog bulk potential tracking method, makes MOS transistors from different stages exhibit about the same body effect, which is very important because MOS transistors of higher order stages now show the same performance as MOS transistors from lower order stages.

Abstract: A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum.

Abstract: A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an address end. The first encoder encodes the testing data to the data type of the first data end according to the testing address. The second encoder encodes the testing data to the data type of the second data end according to the testing address. In this way, the corresponding memory cells of the first data and second ends store same testing data.

Abstract: A trigger circuit for triggering corresponding memory cells of a column redundant circuit includes a determining circuit for generating a determining signal according to an accessed row address, and a plurality of comparing circuits jointly electrically connected to the column redundant circuit for receiving the determining signal, each of the comparing circuits selectively generating a trigger signal to the column redundant circuit according to the determining signal and an accessed column address.

Abstract: The invention discloses a charge pump circuit control system comprising a level detector, a ring oscillator, and a charge pump circuit. The level detector detects the variation of the output voltage of the charge pump circuit for generating a control signal. The ring oscillator generates a plurality of clock signals according to the control signal, and the charge pump circuit generates the output voltage according to the plurality of clock signals.

Abstract: A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum.

Abstract: The invention discloses a decoupling capacitor circuit, comprising a plurality of coupled deep trench capacitors connected in series and a plurality of push-pull circuits. The decoupling capacitor circuit controls the voltage across each deep trench capacitor via the push-pull circuit so that it will not be influenced by the defect (leakage current) of the deep trench capacitor or the bias voltage of the parasitic devices.

Abstract: A negative voltage generator includes a current mirror unit, a control unit, a resistor, and a switching unit. The current mirror unit receives a first positive voltage from a first positive voltage source and a second positive voltage from a second positive voltage source and determines how to generate a first output current and a second output current according to the difference of a received positive reference voltage and the second positive voltage. The control unit generates a control signal whose value depends on the voltage variation of a negative voltage generated by a negative voltage source, and the on/off state of the switching unit is determined according to the control signal to keep the current passing through the switching unit constant and to generate a first output negative voltage having a constant level.

Abstract: A built-in calibration device is for a temperature sensor. A voltage divider is configured for receiving one reference voltage with a negative temperature coefficient and generating a plurality of input voltages. Comparing apparatus is connected to the voltage divider and configured for generating a plurality of comparing codes based upon another reference voltage with a positive temperature coefficient and the plurality of input voltages. Controlling apparatus is connected to the comparing apparatus and configured for calibrating the temperature sensor based on the plurality of comparing codes.

Abstract: A circuit and method are given, to realize a high efficiency voltage multiplier for integrated circuits generating an internal and flexible positive or negative high voltage on-chip supply voltage from low external positive or negative supply voltages or ground. Applying multi-phase control signals to voltage boost internal nodes allows for eliminating threshold voltage drop losses and thus improves the voltage pumping gain compared to circuits with diode-configured FETs of prior art. Making use of voltage signals from antecedent stages in order to bias the bulk of MOS transistors fabricated in triple-well technology enables relaxing of the gate oxide stress within high order stage MOS transistors. Such a method, called leap-frog bulk potential tracking method, makes MOS transistors from different stages exhibit about the same body effect, which is very important because MOS transistors of higher order stages now show the same performance as MOS transistors from lower order stages.

Abstract: The invention discloses a decoupling capacitor circuit, comprising a plurality of coupled deep trench capacitors connected in series and a plurality of push-pull circuits. The decoupling capacitor circuit controls the voltage across each deep trench capacitor via the push-pull circuit so that it will not be influenced by the defect (leakage current) of the deep trench capacitor or the bias voltage of the parasitic devices.

Abstract: The invention discloses a charge pump circuit control system comprising a level detector, a ring oscillator, and a charge pump circuit. The level detector detects the variation of the output voltage of the charge pump circuit for generating a control signal. The ring oscillator generates a plurality of clocksignals according to the control signal. And the charge pump circuit generates the output voltage according to the plurality of clock signals.

Abstract: A negative voltage generator includes a current mirror unit, a control unit, a resistor, and a switching unit. The current mirror unit receives a first positive voltage from a first positive voltage source and a second positive voltage from a second positive voltage source and determines how to generate a first output current and a second output current according to the difference of a received positive reference voltage and the second positive voltage. The control unit generates a control signal whose value depends on the voltage variation of a negative voltage generated by a negative voltage source, and the on/off state of the switching unit is determined according to the control signal to keep the current passing through the switching unit constant and to generate a first output negative voltage having a constant level.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: Methods and circuits to reduce power consumption of DRAM local word-line drivers are disclosed. A first voltage converter provides a voltage VPP1, which is lower than the voltage VPP required to operate a word-line of a DRAM cell array. A voltage detector monitors the voltage level of the local word-line driver. Once the voltage level VPP1 is reached on the local word-linedriver switching means as e.g. tri-state drivers put the final VPP voltage on the word line. This VPP voltage is the output of a second voltage boost converter. Putting the voltage in two stages on the word-line reduces the overall power consumption. The voltage level VPP1 has to be carefully selected to find a compromised solution between current consumption and performance.

Abstract: A built-in calibration device is for a temperature sensor. A voltage divider is configured for receiving one reference voltage with a negative temperature coefficient and generating a plurality of input voltages. Comparing apparatus is connected to the voltage divider and configured for generating a plurality of comparing codes based upon another reference voltage with a positive temperature coefficient and the plurality of input voltages. Controlling apparatus is connected to the comparing apparatus and configured for calibrating the temperature sensor based on the plurality of comparing codes.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power where the large capacity power source is turned off, and the memory chip internal voltages are provided by a small capacity power source. Switching between the standby and active states of the low power memory chip is accomplished by turning on and off a standby signal. The internal and external chip voltages are monitored during chip power up to insure that predetermined voltage levels have been reached before turning off the large capacity power source and placing the chip into a standby state.

Abstract: An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power where the large capacity power source is turned off, and the memory chip internal voltages are provided by a small capacity power source. Switching between the standby and active states of the low power memory chip is accomplished by turning on and off a standby signal. The internal and external chip voltages are monitored during chip power up to insure that predetermined voltage levels have been reached before turning off the large capacity power source and placing the chip into a standby state.