Abstract: A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

Abstract: A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a meshed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the meshed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes.

Abstract: A circuit structure with a capacitor or a resistor includes a semiconductor substrate, a first conductive region positioned in the semiconductor substrate, a plurality of second conductive regions and third conductive regions positioned in the first conductive region, a first depletion region positioned between the first conductive region and the third conductive region, a second depletion region positioned between the second conductive region and the third conductive region, and a plurality of separating regions positioned in the first conductive region, configured to separate the second and the third conductive regions. In operation, a first voltage is applied to the separating region to control the capacitance or the resistance of the circuit structure. A second voltage is applied to the first conductive region and a third voltage is applied to the second conductive region to measure the capacitance and the resistance of the circuit structure.

Abstract: A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.

Abstract: A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

Abstract: A method for fabricating an integrated device with reduced plasma damage is disclosed, including providing a substrate, forming a structural layer on the substrate, forming a photoresist layer on the structural layer, and performing an etching process to the structural layer, wherein the photoresist layer is conductive to reduce plasma damage during the etching process.

Abstract: The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate.

Abstract: A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a mashed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the mashed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes.

Abstract: A wafer scrubber apparatus is disclosed, including a chamber, and holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and a gas purge pipe disposed at the top of a wall of the chamber, wherein the gas purge pipe comprises a plurality of gas injection holes facing downward to purge gas along the chamber wall making water flow along the chamber wall more smoothly and more quickly for preventing the water from scattering back to the wafer.

Abstract: A circuit structure with a capacitor or a resistor includes a semiconductor substrate, a first conductive region positioned in the semiconductor substrate, a plurality of second conductive regions and third conductive regions positioned in the first conductive region, a first depletion region positioned between the first conductive region and the third conductive region, a second depletion region positioned between the second conductive region and the third conductive region, and a plurality of separating regions positioned in the first conductive region, configured to separate the second and the third conductive regions. In operation, a first voltage is applied to the separating region to control the capacitance or the resistance of the circuit structure. A second voltage is applied to the first conductive region and a third voltage is applied to the second conductive region to measure the capacitance and the resistance of the circuit structure.

Abstract: A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.

Abstract: A method for forming a contact of a semiconductor device with reduced step height is disclosed, comprising forming a plurality of gates, forming a buffer layer on each of the gates, forming an insulating layer to fill spaces between the gates, forming strip-shaped photoresist patterns which cross the gates, etching the insulating layer to form first openings using a self-aligning process with the gates and the strip-shaped photoresist patterns as a mask, forming a conductive contact layer to fill the first openings, performing a first chemical mechanical polish (CMP) process to the conductive contact layer, removing the buffer layer, and forming a second chemical mechanical polish (CMP) process to the conductive contact layer.