Abstract: A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated.

Abstract: A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: The invention discloses a signal converting device, and more particularly, to a signal converting device that improves the signal quality. The signal converting device comprises a first input end, a second input end, an output end, a first circuit and a second circuit. The first circuit is coupled between the first input end and the output end. The first circuit determines whether to charge up the output end to generate an output signal or not according to a first differential input signal. The second circuit is coupled between the second input end and the output end. The second circuit determines whether to discharge the output end to generate the output signal or not according to a second differential input signal.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A fuse circuit comprises at least one fuse circuit unit and a current blocking module. The fuse circuit unit comprises a voltage establishing module and a latch. The voltage establishing module is coupled to a first reference voltage source and includes a fuse that is capable of being selectively blown according to an initial setting signal. The fuse has a first terminal coupled to a node and a second terminal. The voltage establishing module establishes a voltage level on the node according to the blown-off status of the fuse. The latch is coupled to the voltage establishing module through the node for latching the voltage level of the node and generating the output signal. The current blocking module is coupled between a second reference voltage source and the second terminal of the fuse for blocking the current flowing through the fuse while initial setting.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A fuse circuit comprises at least one fuse circuit unit and a current blocking module. The fuse circuit unit comprises a voltage establishing module and a latch. The voltage establishing module is coupled to a first reference voltage source and includes a fuse that is capable of being selectively blown according to an initial setting signal. The fuse has a first terminal coupled to a node and a second terminal. The voltage establishing module establishes a voltage level on the node according to the blown-off status of the fuse. The latch is coupled to the voltage establishing module through the node for latching the voltage level of the node and generating the output signal. The current blocking module is coupled between a second reference voltage source and the second terminal of the fuse for blocking the current flowing through the fuse while initial setting.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A blocking section is inserted between the control section and the fuse section of a fuse control logic circuit. The blocking section comprises switching means which block the flow of DC current during a power-up sequence and thus avoids the collapse of the power supply voltage with the attending potential for incorrect addressing and improper function and timing options. The insertion of the blocking section further eliminates indeterminate logic states when fusible means are not fully blown thus assuring correct voltage levels at the output of the circuit.

Abstract: A blocking section is inserted between the control section and the fuse section of a fuse control logic circuit. The blocking section comprises switching means which block the flow of DC current during a power-up sequence and thus avoids the collapse of the power supply voltage with the attending potential for incorrect addressing and improper function and timing options. The insertion of the blocking section further eliminates indeterminate logic states when fusible means are not fully blown thus assuring correct voltage levels at the output of the circuit.

Abstract: A memory device with burn-in capability is achieved. The device comprises, first, an array of memory cells, and, second, a burn-in test block. The burn-in test block comprises a memory address generator, a data pattern generator, and a command pattern generator. The burn-in test block is capable of writing data to the memory cells, of turning ON word lines in the array, and of holding the array in a static mode. A method to perform wafer level burn-in with this device is disclosed.

Abstract: A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells, wherein the dynamic memory cells require periodic refreshing, is achieved. The method comprises, first, determining if an external access to the dynamic memory array has been initiated. Second, a waiting period of RW idle time is inserted. The RW idle time comprises a sum of a row access time plus a pre-charge time. A pending refresh is performed during said RW idle time. A pending write access may be performed during the RW idle time. Finally, the external access is internally executed in the dynamic memory array after the RW idle time.

Abstract: A minimum pulse width detection and regeneration circuit is achieved. The circuit includes, first, a pulse width detector capable of detecting if an input signal pulse is within a range between a minimum width and a maximum width. Second, a pulse width extender is capable of extending the input signal pulse width to the maximum width if the input signal pulse is in the range. Finally, a glitch filter is capable of filtering out the input signal pulse if the input signal pulse is less than the minimum width.

Abstract: An input buffer receiver is described that will latch on a particular transition to insure a single transition does not have multiple transitions due to disturbances. This is accomplished with a Schmitt Trigger and a feedback latch controlled by an enabling signal. In one application, this is a chip select. A chip addressing input to a Schmitt Trigger type tri-state buffer is applied in parallel to two gates of the plurality of stacked CMOS transistors. A chip selection (CSB) signal is applied to a first gate of the Schmitt Trigger type tri-state buffer and in parallel to a second gate through an inverter. The output of the tri-state buffer is then fed to a latch circuit comprised of a plurality of stacked CMOS transistors. The latch output is the signal that goes to the circuitry that selects the desired chip address. The latch output is fed back into the appropriate gates of the latch to effect the desired latch-up when the Schmitt Trigger is put into the high output impedance state.

Abstract: A delay circuit that is insensitive to variations in an input signal voltage level has a voltage clamp at its input terminal to fix the input voltage level so as to remove the sensitivity of the delay circuit to the variations in the input signal voltage level and the power supply voltage source. A voltage independent delay circuit is composed of a first inverter circuit, a voltage clamping circuit, a delay capacitor, and a second inverter circuit. The first inverter circuit has an input terminal and an output terminal. A first output signal at the output terminal is an inverse of an input signal at the input terminal. The voltage clamping circuit is connected between the output terminal and the input terminal of the first inverter circuit to fix a voltage swing of input signal to a first voltage level. The delay capacitor connected to the output terminal of the first inverter to establish a transition time of the first output signal.

Abstract: In this invention a global row redundancy scheme for a DRAM is described which effectively uses the resources of the chip to produce an area efficient design. The DRAM is constructed from two types of memory blocks, one that has a redundant cell array and one that does not. Both memory block types contain a memory cell array and bit line sense amplifiers. The bit line sense amplifiers, contained on the block with the redundant cell array, are shared with the memory cell array also contained in the block, and thus eliminating the need for sense amplifiers for use only with the redundant cell array. Although, every block could contain a redundant cell array, only one or two blocks with the redundant cell array are normally used.

Abstract: Methods and circuits are disclosed for a semiconductor memory that allow one or more clock cycles per memory write operation, which allow the memory clock cycle time to be varied, and which minimize power dissipation. This is achieved by providing circuits that generate a minimum internal write time reference, independent of the chosen clock cycle time, so that a memory write cycle might take one clock cycle, or more than one clock cycle if the clock cycle is shortened.

Abstract: A high speed conditional synchronous one-shot circuit includes a master flip-flop for receiving an input signal and a clock signal and generating an output signal in response to the input signal and holding the output signal while the clock signal is high, the output signal going low upon the clock signal going low. A slave flip-flop has an input for receiving the output signal from the first flip-flop and a reset terminal for receiving a reset signal when the clock signal is low, a second flip-flop generating an output signal when the clock signal is high and in response to the output signal from the first flip-flop. In another embodiment, the one-shot circuit comprises a plurality of NAND gates, each gate having a plurality of inputs and an output.