Patents by Inventor Jenifer E. Lary
Jenifer E. Lary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9496110Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and usage, and design structures are disclosed herein. The method includes applying a first voltage polarity to an actuator of a Micro-Electro-Mechanical System (MEMS) structure to place the MEMS structure in a predetermined state for a first operating condition. The method further includes applying a second voltage polarity which is opposite from the first voltage polarity to the actuator of the MEMS structure during a subsequent operating condition.Type: GrantFiled: June 18, 2013Date of Patent: November 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ward A. Johnson, Jenifer E. Lary, Anthony K. Stamper, Kimball M. Watson, Pui L. Yee
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Publication number: 20140368292Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and usage, and design structures are disclosed herein. The method includes applying a first voltage polarity to an actuator of a Micro-Electro-Mechanical System (MEMS) structure to place the MEMS structure in a predetermined state for a first operating condition. The method further includes applying a second voltage polarity which is opposite from the first voltage polarity to the actuator of the MEMS structure during a subsequent operating condition.Type: ApplicationFiled: June 18, 2013Publication date: December 18, 2014Inventors: Ward A. Johnson, Jenifer E. Lary, Anthony K. Stamper, Kimball M. Watson, Pui L. Yee
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Patent number: 8421181Abstract: A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region.Type: GrantFiled: July 21, 2010Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Frederick G. Anderson, Jenifer E. Lary, Robert M. Rassel, Mark E. Stidham
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Patent number: 8384140Abstract: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.Type: GrantFiled: July 29, 2008Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Patent number: 8198663Abstract: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.Type: GrantFiled: July 29, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Publication number: 20120018837Abstract: A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region.Type: ApplicationFiled: July 21, 2010Publication date: January 26, 2012Applicant: International Business Machines CoporationInventors: Frederick G. Anderson, Jenifer E. Lary, Robert M. Rassel, Mark E. Stidham
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Patent number: 7897473Abstract: A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench.Type: GrantFiled: July 29, 2008Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Patent number: 7759189Abstract: A method of manufacturing a dual contact trench capacitor is provided. The method includes a first plate extending from a trench and isolated from a wafer body, and forming a second plate extending from the trench and isolated from the wafer body and the first plate.Type: GrantFiled: July 29, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Publication number: 20100029056Abstract: A method of manufacturing a dual contact trench capacitor is provided. The method includes a first plate extending from a trench and isolated from a wafer body, and forming a second plate extending from the trench and isolated from the wafer body and the first plate.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Publication number: 20100025814Abstract: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Publication number: 20100025813Abstract: A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Publication number: 20100029055Abstract: A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Timothy W. Kemerer, Jenifer E. Lary, James S. Nakos, Steven M. Shank
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Publication number: 20040092109Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.Type: ApplicationFiled: October 31, 2003Publication date: May 13, 2004Applicant: International Business Machines CorporationInventors: Eric Adler, James S. Dunn, Joseph Iadanza, Jenifer E. Lary
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Patent number: 6683345Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.Type: GrantFiled: December 20, 1999Date of Patent: January 27, 2004Assignee: International Business Machines, Corp.Inventors: Eric Adler, James S. Dunn, Joseph Iadanza, Jenifer E. Lary, Kent E. Morrett, Josef S. Watts
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Patent number: 6433372Abstract: A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.Type: GrantFiled: March 17, 2000Date of Patent: August 13, 2002Assignee: International Business Machines CorporationInventors: Eric Adler, Kerry Bernstein, John J. Ellis-Monaghan, Jenifer E. Lary, Edward J. Nowak, Norman J. Rohrer
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Patent number: 5534732Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.Type: GrantFiled: December 4, 1995Date of Patent: July 9, 1996Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Jenifer E. Lary, Edmund J. Sprogis