Patents by Inventor Jenn-Hwa Huang
Jenn-Hwa Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11784236Abstract: Methods of fabricating a semiconductor device include providing a semiconductor substrate that includes a plurality of epitaxial layers, including a channel layer and a permanent cap over the channel layer, where the permanent cap defines an upper surface of the semiconductor substrate, and forming a sacrificial cap over the permanent cap in an active region of the device, where the sacrificial cap comprises a semiconductor material that includes aluminum. The method also includes forming one or more current carrying regions (e.g., source and drain regions) in the semiconductor substrate in the active region of the device by performing an ion implantation process to implant ions through the sacrificial cap, and into the semiconductor substrate, completely removing the sacrificial cap in the active region of the device, while refraining from removing the permanent cap, and forming one or more current carrying contacts over the one or more current carrying regions.Type: GrantFiled: September 29, 2020Date of Patent: October 10, 2023Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, Yuanzheng Yue, Bruce Mcrae Green, Karen Elizabeth Moore, James Allen Teplik
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Publication number: 20220102529Abstract: Methods of fabricating a semiconductor device include providing a semiconductor substrate that includes a plurality of epitaxial layers, including a channel layer and a permanent cap over the channel layer, where the permanent cap defines an upper surface of the semiconductor substrate, and forming a sacrificial cap over the permanent cap in an active region of the device, where the sacrificial cap comprises a semiconductor material that includes aluminum. The method also includes forming one or more current carrying regions (e.g., source and drain regions) in the semiconductor substrate in the active region of the device by performing an ion implantation process to implant ions through the sacrificial cap, and into the semiconductor substrate, completely removing the sacrificial cap in the active region of the device, while refraining from removing the permanent cap, and forming one or more current carrying contacts over the one or more current carrying regions.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Inventors: Jenn Hwa Huang, Yuanzheng Yue, Bruce McRae Green, Karen Elizabeth Moore, James Allen Teplik
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Patent number: 10971613Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: GrantFiled: March 30, 2020Date of Patent: April 6, 2021Assignee: NXP USA, Inc.Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
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Patent number: 10957790Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: GrantFiled: December 31, 2018Date of Patent: March 23, 2021Assignee: NXP USA, Inc.Inventors: Bruce McRae Green, Darrell Glenn Hill, Karen Elizabeth Moore, Jenn-Hwa Huang, Yuanzheng Yue, James Allen Teplik, Lawrence Scott Klingbeil
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Patent number: 10741496Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.Type: GrantFiled: December 4, 2018Date of Patent: August 11, 2020Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, James Allen Teplik, Darrell Glenn Hill
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Publication number: 20200227547Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: ApplicationFiled: March 30, 2020Publication date: July 16, 2020Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
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Patent number: 10692976Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.Type: GrantFiled: February 1, 2017Date of Patent: June 23, 2020Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, Weixiao Huang
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Publication number: 20200176389Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Inventors: Jenn Hwa Huang, James Allen Teplik, Darrell Glenn Hill
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Patent number: 10644142Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: GrantFiled: December 22, 2017Date of Patent: May 5, 2020Assignee: NXP USA, Inc.Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
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Patent number: 10403718Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.Type: GrantFiled: December 28, 2017Date of Patent: September 3, 2019Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, Yuanzheng Yue
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Patent number: 10355085Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.Type: GrantFiled: December 28, 2017Date of Patent: July 16, 2019Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, Yuanzheng Yue
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Publication number: 20190206998Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Jenn Hwa Huang, Yuanzheng Yue
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Publication number: 20190206994Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Jenn Hwa Huang, Yuanzheng Yue
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Publication number: 20190198623Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
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Publication number: 20190157440Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: ApplicationFiled: December 31, 2018Publication date: May 23, 2019Inventors: Bruce McRae Green, Darrell Glenn Hill, Karen Elizabeth Moore, Jenn-Hwa Huang, Yuanzheng Yue, James Allen Teplik, Lawrence Scott Klingbeil
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Patent number: 9972703Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: GrantFiled: August 1, 2016Date of Patent: May 15, 2018Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, James A. Teplik
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Patent number: 9893156Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: GrantFiled: March 28, 2017Date of Patent: February 13, 2018Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
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Patent number: 9871107Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.Type: GrantFiled: May 22, 2015Date of Patent: January 16, 2018Assignee: NXP USA, INC.Inventors: Bruce M. Green, Jenn Hwa Huang, Vikas S. Shilimkar
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Patent number: 9799760Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: GrantFiled: August 17, 2015Date of Patent: October 24, 2017Assignee: NXP USA, INC.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Publication number: 20170200794Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: JENN HWA HUANG, TIANWEI SUN, JAMES A. TEPLIK