Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with relative humidity (RH) sensors are described. Examples can include receiving from an RH sensor RH information of an environment of a processing resource or a memory resource coupled to the processing resource, or both, determining that the RH information indicates an RH level above a particular threshold for the processing resource or the memory resource, or both, and disabling one or more aspects of the processing resource or the memory resource, or both, to mitigate damage to the processing resource or the memory resource, or both, responsive to determining that the RH is above the particular threshold.

Abstract: Methods, devices, and systems related to a wearable monitor with memory are described. An example device may include an electrode integrated into a multi-chip package (MCP) memory device, the electrode to monitor health data of a wearer of the wearable monitor. The device can include a first processing resource coupled to the MCP memory device, the electrode, or both, to receive the monitored health data. The MCP memory device may store the received health data. The MCP memory device may also be coupled to a wireless communication device. The wireless communication device may transfer the stored health data to a computing device. The computing device may be communicatively coupled to the example device.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with relative humidity (RH) sensors are described. Examples can include receiving from an RH sensor RH information of an environment of a processing resource or a memory resource coupled to the processing resource, or both, determining that the RH information indicates an RH level above a particular threshold for the processing resource or the memory resource, or both, and disabling one or more aspects of the processing resource or the memory resource, or both, to mitigate damage to the processing resource or the memory resource, or both, responsive to determining that the RH is above the particular threshold.

Abstract: A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

Abstract: A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

Abstract: A circuit and method of operation for combining commands in a DRAM (dynamic random access memory) are revealed. The method applies to DRAMs having a plurality of memory banks or arrays. The method combines commands to rows on different memory banks, and the method also combines row and column commands on different memory banks. The method eliminates steps in a sequence of commands, and may significantly increase speed of input/output to a DRAM.