Patents by Inventor Jennifer Yuan

Jennifer Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240067939
    Abstract: The present disclosure provides methods, compositions, kits and systems for nucleic acid amplification. In some embodiments, nucleic acid amplification methods include subjecting the nucleic acid to be amplified to partially denaturing conditions. In some embodiments, nucleic acid amplification methods include amplifying without fully denaturing the nucleic acid that is amplified. In some embodiments, the nucleic acid amplification method employs an enzyme that catalyzes homologous recombination and a polymerase. In some embodiments, methods for nucleic acid amplification can be conducted in a single reaction vessel and/or in a single continuous liquid phase of a reaction mixture, without need for compartmentalization of the reaction mixture or immobilization of reaction components.
    Type: Application
    Filed: July 12, 2023
    Publication date: February 29, 2024
    Inventors: Chieh-Yuan LI, David RUFF, Shiaw-Min CHEN, Jennifer O'NEIL, Rachel KASINSKAS, Jonathan ROTHBERG, Bin LI, Kai Qin LAO
  • Patent number: 8265058
    Abstract: A method and an apparatus to select a route in a network device within a networked system have been disclosed. In one embodiment, the method includes receiving at a router in a Border Gateway Protocol (BGP) network a first route entry via local redistribution from a first protocol to BGP and a second route entry from a peer router coupled to the router via the network, wherein the first route entry is received earlier than the second route entry. The method may further include downloading administrative distances of the first and the second route entries to a route information base (RIB) of the router and redistributing the administrative distances from the RIB to a BGP table maintained by a BGP module of the router. In some embodiments, the method further includes selecting one of the first and the second route entries based on their administrative distances.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: September 11, 2012
    Assignee: Ericsson AB
    Inventors: Enke Chen, Jennifer Yuan
  • Publication number: 20050174989
    Abstract: A method and an apparatus to select a route in a network device within a networked system have been disclosed. In one embodiment, the method includes receiving at a router in a Border Gateway Protocol (BGP) network a first route entry via local redistribution from a first protocol to BGP and a second route entry from a peer router coupled to the router via the network, wherein the first route entry is received earlier than the second route entry. The method may further include downloading administrative distances of the first and the second route entries to a route information base (RIB) of the router and redistributing the administrative distances from the RIB to a BGP table maintained by a BGP module of the router. In some embodiments, the method further includes selecting one of the first and the second route entries based on their administrative distances.
    Type: Application
    Filed: January 14, 2005
    Publication date: August 11, 2005
    Inventors: Enke Chen, Jennifer Yuan
  • Patent number: 5889829
    Abstract: A phase-locked loop (PLL) circuit is used to synchronize a local clock frequency with an edge of a reference clock frequency, employing a phase detector to compare the local clock frequency and the reference clock frequency to generate a control signal indicative of the need to increase or to decrease the local clock frequency for phase locking thereof to the reference clock frequency. A voltage controlled oscillator (VCO) is responsive to a signal voltage derived from the control signal to vary the local clock frequency as necessary to achieve phase locking. A loop filter has a reference voltage threshold level which is pre-programmable to enable the loop filter to respond to the control signal by adjusting the signal voltage as a virtual step function toward the programmed reference voltage threshold level before application to the VCO, and then cycling up and down in a search for a stable control signal voltage to reduce the time necessary to achieve the desired phase locking.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: March 30, 1999
    Assignee: Microchip Technology Incorporated
    Inventors: Jennifer Yuan Chiao, Randy L. Yach
  • Patent number: 5874863
    Abstract: A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: February 23, 1999
    Assignee: Microchip Technology Incorporated
    Inventors: Igor Wojewoda, Jennifer Yuan Chiao