Abstract: This disclosure relates to radio frequency (RF) functional testing of transceivers of wireless devices.

Abstract: A multi-standard transceiver includes a first subunit configured to perform signal processing according to a first communication standard and a second subunit configured to perform signal processing according to a second communication standard. Furthermore, the multi-standard transceiver includes an interference cancellation unit configured to drive an estimated interference signal from a first signal generated by the first subunit by performing the signal processing according to the first communication standard, and perform interference cancellation on a second signal generated by the second subunit by performing the signal processing according to the second communication standard based on the estimated interference signal.

Abstract: An assembly includes a support element and a chip having contact elements. The chip is mounted onto the support element with the contact elements facing the support element. A shield layer is on the support element for electrically or magnetically shielding a circuit element of the chip.

Abstract: A multi-standard transceiver includes a first subunit configured to perform signal processing according to a first communication standard and a second subunit configured to perform signal processing according to a second communication standard. Furthermore, the multi-standard transceiver includes an interference cancellation unit configured to drive an estimated interference signal from a first signal generated by the first subunit by performing the signal processing according to the first communication standard, and perform interference cancellation on a second signal generated by the second subunit by performing the signal processing according to the second communication standard based on the estimated interference signal.

Abstract: Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Abstract: Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Abstract: Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Abstract: This disclosure relates to radio frequency (RF) functional testing of transceivers of wireless devices.

Abstract: A first signal path having an amplifier and a second signal path having an amplifier with adjustable gain factor are provided. A signal applied to the first and second signal paths is amplified and demodulated on the first signal path. Concurrently, the signal is amplified on the second signal path with a gain factor, and a power of the signal amplified by the second signal path is determined and used for determining the gain factor. A signal conditioning circuit has first and second signal paths and a first and a second operating state. In the first operating state, the first signal path is arranged for amplification for a demodulation, and the second signal path is arranged for amplification for determination of a power of the signal present. In the second operating state, one of the two signal paths is inactive and the other is arranged for demodulating the signal present.

Abstract: An assembly includes a support element and a chip having contact elements. The chip is mounted onto the support element with the contact elements facing the support element. A shield layer is on the support element for electrically or magnetically shielding a circuit element of the chip.

Abstract: A first signal path having an amplifier and a second signal path having an amplifier with adjustable gain factor are provided. A signal applied to the first and second signal paths is amplified and demodulated on the first signal path. Concurrently, the signal is amplified on the second signal path with a gain factor, and a power of the signal amplified by the second signal path is determined and used for determining the gain factor. A signal conditioning circuit has first and second signal paths and a first and a second operating state. In the first operating state, the first signal path is arranged for amplification for a demodulation, and the second signal path is arranged for amplification for determination of a power of the signal present. In the second operating state, one of the two signal paths is inactive and the other is arranged for demodulating the signal present.