Patents by Inventor Jeong Byun

Jeong Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180258452
    Abstract: The present invention relates to an L-lysine-producing microorganism of the genus Corynebacterium and a method for producing L-lysine using the same.
    Type: Application
    Filed: July 27, 2016
    Publication date: September 13, 2018
    Inventors: Hyo Jeong BYUN, Yoon Hee CHUNG, Hyung Joon KIM, Sun Young LEE, Hyun Koo NAM, Sun Mi PARK, Sang Mok LEE
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Patent number: 8592891
    Abstract: A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: November 26, 2013
    Assignee: Cypress Semiconductor Corp.
    Inventors: Igor Polishchuk, Sagy Levy, Krishnaswamy Ramkumar, Jeong Byun
  • Publication number: 20130309826
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Application
    Filed: July 1, 2012
    Publication date: November 21, 2013
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Krishnaswamy RAMKUMAR, Sagy LEVY, Jeong BYUN
  • Patent number: 8318608
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: November 27, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Patent number: 7799670
    Abstract: A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H2) and oxygen (O2) gas mixture into a process chamber and exposing the substrate to a plasma. In a preferred embodiment, a high density plasma (HDP) chamber is employed to oxidize a portion of the charge trapping layer. In further embodiments, a portion of a silicon-rich silicon oxynitride charge trapping layer is consumptively oxidized to form the blocking layer and provide an increased memory window relative to oxidation of a nitrogen-rich silicon oxynitride layer.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: September 21, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Publication number: 20090242962
    Abstract: A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H2) and oxygen (O2) gas mixture into a process chamber and exposing the substrate to a plasma. In a preferred embodiment, a high density plasma (HDP) chamber is employed to oxidize a portion of the charge trapping layer. In further embodiments, a portion of a silicon-rich silicon oxynitride charge trapping layer is consumptively oxidized to form the blocking layer and provide an increased memory window relative to oxidation of a nitrogen-rich silicon oxynitride layer.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Publication number: 20090011609
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.
    Type: Application
    Filed: August 25, 2008
    Publication date: January 8, 2009
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Publication number: 20080014724
    Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes positioning a substrate containing a metal nitride barrier layer within a process chamber and exposing the substrate to a reagent gas containing diborane to form a reagent layer on the metal nitride barrier layer. The method further provides exposing the substrate sequentially to a tungsten precursor and a reductant to form a nucleation layer during an atomic layer deposition (ALD) process and subsequently depositing a bulk layer over the nucleation layer. The bulk layer may contain copper, but generally contains tungsten deposited by a chemical vapor deposition (CVD) process. In some examples, the bulk layer may be used to fill apertures within the substrate.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 17, 2008
    Inventor: Jeong Byun
  • Publication number: 20070254481
    Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.
    Type: Application
    Filed: June 21, 2007
    Publication date: November 1, 2007
    Inventors: MORIS KORI, Alfred Mak, Jeong Byun, Lawrence Lei, Hua Chung, Ashok Sinha, Ming Xi
  • Publication number: 20070197027
    Abstract: In one embodiment, a method for depositing a boride-containing barrier layer on a substrate is provided which includes exposing the substrate sequentially to a boron-containing compound and a metal precursor to form a first boride-containing layer during a first sequential chemisorption process and exposing the substrate to the boron-containing compound, the metal precursor, and a second precursor to form a second boride-containing layer on the first boride-containing layer during a second sequential chemisorption process. In one example, the metal precursor contains tungsten hexafluoride and the boron-containing compound contains diborane. In another embodiment, a contact layer is deposited over the second boride-containing layer. The contact layer may contain tungsten and be deposited by a chemical vapor deposition process. Alternatively, the contact layer may contain copper and be deposited by a physical vapor deposition process.
    Type: Application
    Filed: April 24, 2007
    Publication date: August 23, 2007
    Inventors: Jeong Byun, Alfred Mak
  • Publication number: 20070197028
    Abstract: In one embodiment, a method for depositing a boride-containing barrier layer on a substrate is provided which includes exposing the substrate sequentially to a boron-containing compound and a tungsten precursor to form a first boride-containing layer during a first sequential chemisorption process, and exposing the substrate to the boron-containing compound, the tungsten precursor, and ammonia to form a second boride-containing layer over the first boride-containing layer during a second sequential chemisorption process. In one example, the tungsten precursor contains tungsten hexafluoride and the boron-containing compound contains diborane. In another embodiment, a contact layer is deposited over the second boride-containing layer. The contact layer may contain tungsten and be deposited by a chemical vapor deposition process. Alternatively, the contact layer may contain copper and be deposited by a physical vapor deposition process.
    Type: Application
    Filed: April 24, 2007
    Publication date: August 23, 2007
    Inventors: Jeong Byun, Alfred Mak
  • Publication number: 20060292874
    Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to a first reducing gas and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method may further provide exposing the substrate to a deposition gas comprising a second reducing gas and the tungsten precursor gas to form a tungsten bulk layer on the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples include that the ALD and CVD processes are conducted in the same deposition chamber or in different deposition chambers.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 28, 2006
    Inventors: Moris Kori, Alfred Mak, Jeong Byun, Lawrence Lei, Hua Chung, Ashok Sinha, Ming Xi
  • Publication number: 20060223286
    Abstract: A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer support is movable between the two or more interconnected deposition regions within the deposition chamber.
    Type: Application
    Filed: June 12, 2006
    Publication date: October 5, 2006
    Inventors: Barry Chin, Alfred Mak, Lawrence Lei, Ming Xi, Hua Chung, Ken Lai, Jeong Byun
  • Publication number: 20060211202
    Abstract: A metal suicide layer is formed on silicon-containing features of a substrate in a chamber. A metal film is sputter deposited on the substrate and a portion of the sputter deposited metal film is silicided. In the process, sputtering gas is energized by applying an electrical bias potential across the metal sputtering target and the substrate support to sputter deposit metal from a target onto the substrate. At least a portion of the deposited sputtered metal is silicided by heating the substrate to a silicidation temperature exceeding about 200° C. to form a combined sputtered metal and metal silicide layer on the substrate. The remaining sputtered metal can be silicided by maintaining the substrate at the silicidation temperature to form the metal silicide layer.
    Type: Application
    Filed: March 18, 2005
    Publication date: September 21, 2006
    Inventors: Jeong Byun, Jianxin Lei, Lisa Yang, Hien-Minh Le
  • Publication number: 20060166515
    Abstract: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.
    Type: Application
    Filed: March 24, 2006
    Publication date: July 27, 2006
    Applicant: Applied Materials, Inc.
    Inventors: M. Karim, DongQing Li, Jeong Byun, Thanh Pham
  • Publication number: 20060128132
    Abstract: A method and system to reduce the resistance of refractory metal layers by controlling the presence of fluorine contained therein. The present invention is based upon the discovery that when employing ALD techniques to form refractory metal layers on a substrate, the carrier gas employed impacts the presence of fluorine in the resulting layer. As a result, the method features chemisorbing, onto the substrate, alternating monolayers of a first compound and a second compound, with the second compound having fluorine atoms associated therewith, with each of the first and second compounds being introduced into the processing chamber along with a carrier gas to control a quantity of the fluorine atoms associated with the monolayer of the second compound.
    Type: Application
    Filed: January 24, 2006
    Publication date: June 15, 2006
    Inventors: Ashok Sinha, Ming Xi, Moris Kori, Alfred Mak, Jeong Byun, Lawrence Lei, Hua Chung
  • Publication number: 20060009034
    Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.
    Type: Application
    Filed: January 19, 2005
    Publication date: January 12, 2006
    Inventors: Ken Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Aygerinos Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael Yang, Hua Chung, Jeong Byun
  • Publication number: 20050287807
    Abstract: Methods for the deposition of tungsten films are provided. The methods include depositing a nucleation layer by alternatively adsorbing a tungsten precursor and a reducing gas on a substrate, and depositing a bulk layer of tungsten over the nucleation layer.
    Type: Application
    Filed: August 18, 2005
    Publication date: December 29, 2005
    Inventors: Ken Lai, Jeong Byun, Frederick Wu, Ramanujapuran Srinivas, Avgerinos Gelatos, Mei Chang, Moris Kori, Ashok Sinha, Hua Chung, Hongbin Fang, Alfred Mak, Michael Yang, Ming Xi