Patents by Inventor Jeonghee Shin
Jeonghee Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824795Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.Type: GrantFiled: November 17, 2021Date of Patent: November 21, 2023Inventors: Rohit K. Gupta, Gregory S. Mathews, Harshavardhan Kaushikkar, Jeonghee Shin, Rohit Natarajan
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Publication number: 20230325086Abstract: A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.Type: ApplicationFiled: August 31, 2022Publication date: October 12, 2023Inventors: Anjana Subramanian, Rohit Natarajan, Yu Simon Zhang, Mukul A. Joshi, Harshavardhan Kaushikkar, Jeonghee Shin, Srinivasa Rangan Sridharan
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Publication number: 20230064187Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.Type: ApplicationFiled: November 17, 2021Publication date: March 2, 2023Inventors: Rohit K. Gupta, Gregory S. Mathews, Harshavardhan Kaushikkar, Jeonghee Shin, Rohit Natarajan
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Patent number: 10545739Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.Type: GrantFiled: April 5, 2016Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Patent number: 9858373Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.Type: GrantFiled: July 15, 2015Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Minsik Cho, Brian R. Konigsburg, Jeonghee Shin
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Publication number: 20170286079Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.Type: ApplicationFiled: April 5, 2016Publication date: October 5, 2017Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Patent number: 9665674Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including access to the pipeline, wherein the pipeline access allows the one or more user-defined modules to interact indirectly. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.Type: GrantFiled: May 24, 2016Date of Patent: May 30, 2017Assignee: International Business Machines CorporationInventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Publication number: 20170017747Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.Type: ApplicationFiled: July 15, 2015Publication date: January 19, 2017Inventors: Minsik Cho, Brian R. Konigsburg, Jeonghee Shin
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Publication number: 20160350464Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including access to the pipeline, wherein the pipeline access allows the one or more user-defined modules to interact indirectly. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.Type: ApplicationFiled: May 24, 2016Publication date: December 1, 2016Inventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Patent number: 9507891Abstract: In a computing system running an environment for designing operation of circuity, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.Type: GrantFiled: May 29, 2015Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Patent number: 9477568Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.Type: GrantFiled: September 27, 2013Date of Patent: October 25, 2016Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
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Patent number: 9477797Abstract: In a computing system running an environment for designing operation of circuity, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.Type: GrantFiled: May 29, 2015Date of Patent: October 25, 2016Assignee: International Business Machines CorporationInventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Patent number: 9405866Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.Type: GrantFiled: June 18, 2015Date of Patent: August 2, 2016Assignee: International Business Machines CorporationInventors: Minsik Cho, Brian R. Konigsburg, Indira Nair, Haoxing Ren, Jeonghee Shin
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Publication number: 20150094995Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
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Patent number: 8914764Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: GrantFiled: June 18, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Patent number: 8863068Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: GrantFiled: June 18, 2012Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Patent number: 8826216Abstract: A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.Type: GrantFiled: June 18, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Patent number: 8826203Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: GrantFiled: May 13, 2013Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: John Darringer, Jeonghee Shin
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Publication number: 20140195996Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: ApplicationFiled: June 18, 2012Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin
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Patent number: 8683418Abstract: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.Type: GrantFiled: June 18, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Moinuddin K. Qureshi, Jeonghee Shin