Abstract: Embodiments of the present disclosure relate to a battery pack capable of reducing heat propagation to neighboring cells when an event occurs in a specific battery cell. In an example embodiment, a battery pack includes: a plurality of battery cells; a first heat shielding member arranged to cover a side of a battery cell where a vent is formed; and a rigid member coupled to an outer surface of the first heat shielding member, and the rigid member includes a metal plate and an insulating member covering the metal plate.

Abstract: The present disclosure relates to a battery pack capable of reducing heat propagation to neighboring cells when an event occurs in a specific battery cell. In an example embodiment, a battery pack includes: a plurality of battery cells; a heat shielding member covering a side of a battery cell of the plurality of battery cells where a vent is formed; and a rigid member coupled to an outer surface of the heat shielding member, and the rigid member includes an opening hole corresponding to the vent.

Abstract: The present disclosure provides a secondary battery in which a heat insulation member is attached onto a vent to protect a cell from flames. The secondary battery includes a case having the vent on one side, an electrode assembly in the case, a pair of terminals coupled to respective sides of the case, and electrically connected to the electrode assembly, and the heat insulation member coupled to a surface of the case, and covering a region corresponding to the vent.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: The present technology relates to an electronic device. According to the present technology, a host device may include a garbage collection controller and an idle time processor. The garbage collection controller may provide, to a storage device, a health information request command for requesting health information including a host write amount and a storage device write amount, provide, to the storage device, a first garbage collection control command for requesting garbage collection cost information based on the health information, provide, to the storage device, a second garbage collection control command for instructing to perform garbage collection based on the garbage collection cost information and an idle time of the storage device. The idle time processor may process information on the idle time.

Abstract: Provided herein may be a storage device and a method of operating the same. The method of operating a storage device may include receiving, from an external device, a request to change a set value used for an operation of monitoring an auxiliary power supply of the storage device, changing the set value in response to the request, and performing the operation based on the changed set value.

Abstract: The present technology includes a controller controlling an operation of a semiconductor memory device in response to a test request received from an external device. The controller includes a memory test controller and a performance information storage. The memory test controller generates a command corresponding to a test request received from the external device. The performance information storage stores a test operation result of the semiconductor memory device performed in response to the command.

Abstract: A method of operating a host device according to the present technology includes determining an area to be tested among a mapped area and an unmapped area included in a storage area of a storage device, generating a test request corresponding to the determined area, and transmitting the generated test request to the storage device.

Abstract: A memory system includes a memory device, a memory controller configured to control the memory device, and an auxiliary power source configured to supply power to the memory device and the memory controller. The memory controller activates the auxiliary power source in response to the occurrence an NPO (normal power-off) or an SPO (sudden power-off), checks whether there exists an uncompleted operation at a point of time at which the auxiliary power source is activated, and completes the uncompleted operation, and when an amount of residual energy of the auxiliary power source after completing the uncompleted operation exceeds a predetermined threshold value, performs a data verify operation for a predetermined area in the memory device and stores a result of the data verify operation in the memory device.

Abstract: A system and method for preventing hacking of blockchain is proposed.

Abstract: The present invention relates to compounds of [Formula A]: including N-(9,13b-dihydro-1H-dibenzo[c,f]imidazo[1,5-a]azepin-3-yl)-2-hydroxybenzamide, 2-((9,13b-dihydro-1H-dibenzo[c,f]imidazo[1,5-a]azepin-3-yl)carbamoyl)phenyl acetate, methods for preparing the compounds, and compositions including the compounds as active ingredients. The compounds of the present invention are very effective in anti-inflammation and pain relief. The compositions of the present invention are effective in preventing or treating inflammation and/or pain.

Abstract: A compound having Formula I or its derivative may inhibit metallo-beta-lactamases. An investigation studying the effects of the compounds was provided by the invention of the activities of all subclasses (B1, B2, and B3) metallo-beta-lactamases. The compounds can be used for a pharmaceutical product with the ability to restore an anti-bacterial activity of a beta-lactam antibiotic, thereby treating and preventing a bacterial infection in an animal or human subject.

Abstract: A memory system may include: a memory device suitable for storing data; a controller suitable for controlling the memory device; a power manager suitable for receiving external power, and supplying operation power to the memory device and the controller; and a plurality of auxiliary power circuits suitable for receiving the operation power from the power manager, storing the received power, and supplying auxiliary power to the power manager when the external power is removed. The power manager may group and manage selected auxiliary power circuits among the plurality of auxiliary power circuits as a test group, and perform a full discharge test on the selected auxiliary power circuits.

Abstract: A memory system includes a memory device, a memory controller configured to control the memory device, and an auxiliary power source configured to supply power to the memory device and the memory controller. The memory controller activates the auxiliary power source in response to the occurrence an NPO (normal power-off) or an SPO (sudden power-off), checks whether there exists an uncompleted operation at a point of time at which the auxiliary power source is activated, and completes the uncompleted operation, and when an amount of residual energy of the auxiliary power source after completing the uncompleted operation exceeds a predetermined threshold value, performs a data verify operation for a predetermined area in the memory device and stores a result of the data verify operation in the memory device.

Abstract: A cap for a scalp care container is capable of applying a liquid which is coupled to the scalp care container. The cap includes an upper cap provided with a plurality of bristles, and a lower cap coupled to the upper cap and fastened to the scalp care container.

Abstract: An electronic device may include: a controller; a non-transitory computer-readable storage medium configured to store operation codes for causing the controller to perform operations; and a buffer configured to temporarily store data between a host device and the non-transitory computer-readable storage medium through control of the controller, wherein the operations comprise monitoring a foreground buffer usage rate of the buffer in response to a command of the host device and adjusting a foreground buffer capacity for the command in the buffer, based on the monitored foreground buffer usage rate.

Abstract: A compound having Formula I is an inhibitor of carbapenem-hydrolyzing class D beta-lactamases. The compound inhibits the activities of clinically-important and emerging subgroups of carbapenem-hydrolyzing class D beta-lactamases. A method of treating a bacterial infection includes administering to a subject suffering from a bacterial infection a composition including an effective amount of the compound having Formula I or the pharmaceutically acceptable salt thereof.

Abstract: A compound having Formula I or its derivative may inhibit metallo-beta-lactamases. An investigation studying the effects of the compounds was provided by the invention of the activities of all subclasses (B1, B2, and B3) metallo-beta-lactamases. The compounds can be used for a pharmaceutical product with the ability to restore an anti-bacterial activity of a beta-lactam antibiotic, thereby treating and preventing a bacterial infection in an animal or human subject.

Abstract: A compound having Formula I is an inhibitor of carbapenem-hydrolyzing class D beta-lactamases. The compound inhibits the activities of clinically-important and emerging subgroups of carbapenem-hydrolyzing class D beta-lactamases. A method of treating a bacterial infection includes administering to a subject suffering from a bacterial infection a composition including an effective amount of the compound having Formula I or the pharmaceutically acceptable salt thereof.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The method includes: allocating a first buffer region to a first workload group; allocating a second buffer region to a second workload group; monitoring a first workload group latency and a second workload group latency; and dynamically adjusting a memory space of each of the first and second buffer regions based on a result of the monitoring.