Abstract: Provided are a system for business process automation and a method thereof. The system according to some embodiments may include a connect manager configured to register and manage application programming interface (API) information for services, a process execution engine configured to execute a target business process comprising a particular service task, which is a task using a particular service provided by a service module, and a connect broker configured to acquire API information for the particular service, registered through the connect manager, during execution of the target business process in response to a request from the process execution engine, and process the particular service task by sending a request for the particular service to the service module using the acquired API information.

Abstract: A display device includes a glass substrate including a first surface, a second surface opposite to the first surface, and a side surface between the first and second surfaces, an outermost structure disposed on the first surface and adjacent to an edge of the glass substrate, and a display area including a plurality of emission areas spaced apart from the edge on the first surface of the glass substrate. The side surface has a curved shape with the edge protruding to an outermost side of the glass substrate, the side surface includes a first side surface between the edge and the first surface, and a second side surface between the edge and the second surface and having a different curvature from the first side surface, and the glass substrate includes an edge area on the first surface, adjacent to the edge, and, in which processing traces are left.

Abstract: A semiconductor process chamber includes a susceptor, a base plate surrounding the susceptor, a liner on an inner sidewall of the base plate, and a preheat ring between the susceptor and the base plate and coplanar with the susceptor. The process chamber further includes an upper dome coupled to the base plate and covering an upper surface of the susceptor. The upper dome includes a first section on an upper surface of the base plate and a second section extending from the first section and overlapping the susceptor. The first section includes a first region on the upper surface of the base plate, a second region extending from the first region past the base plate, and a third region extending from the second region with a decreasing thickness to contact the second section.

Abstract: Provided is a computing technology for controlling information display of an electronic shelf label that is connected to a management server via a network and displays electronic information. The electronic shelf label measures a distance to at least one product arranged behind the electronic shelf label, and when a change in the distance occurs, activates a wireless tag reader. When product identification information acquired by the wireless tag reader is different from currently displayed product identification information, the electronic shelf labels request a label change registration to a server. Changed product information is received according to the label change registration, and the changed product information is reflected in displayed product information.

Abstract: Provided is a computing technology for controlling information display of an electronic shelf label that is connected to a management server via a network and displays electronic information. The electronic shelf label measures a distance to at least one product arranged behind the electronic shelf label, and when a change in the distance occurs, activates a wireless tag reader. When product identification information acquired by the wireless tag reader is different from currently displayed product identification information, the electronic shelf labels request a label change registration to a server. Changed product information is received according to the label change registration, and the changed product information is reflected in displayed product information.

Abstract: A semiconductor includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern, the source/drain pattern being in contact with the sheet patterns, and gate structures on opposite sides of the source/drain pattern, the gate structures being spaced apart from each other along a second direction and including gate electrodes that surround the sheet patterns, wherein the source/drain pattern includes a first epitaxial region having at least one of antimony and bismuth, the first epitaxial region having a bottom part in contact with the lower pattern, but not with the sheet patterns, and a thickness of the bottom part increasing and decreasing away from the gate structures in the second direction, and a second epitaxial region on the first epitaxial region, the second epitaxial region including phosphorus.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a memory block including a plurality of pages, a voltage generator configured to generate a program voltage or a verify voltage applied to a selected page among the plurality of pages, a page buffer connected to the selected page through bit lines and configured to perform a precharge operation, an evaluation operation, and a sensing operation on the bit lines during a verify operation, and a control circuit configured to store page addresses of slow pages of which a program operation speed for each is slower than an average program speed of the plurality of pages, and adjust an evaluation time of the evaluation operation according to the page addresses.

Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a memory block including a plurality of pages, a voltage generator configured to generate a program voltage or a verify voltage applied to a selected page among the plurality of pages, a page buffer connected to the selected page through bit lines and configured to perform a precharge operation, an evaluation operation, and a sensing operation on the bit lines during a verify operation, and a control circuit configured to store page addresses of slow pages of which a program operation speed for each is slower than an average program speed of the plurality of pages, and adjust an evaluation time of the evaluation operation according to the page addresses.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: Provided is a computing technology for controlling information display of an electronic shelf label that is connected to a management server via a network and displays electronic information. The electronic shelf label measures a distance to at least one product arranged behind the electronic shelf label, and when a change in the distance occurs, activates a wireless tag reader. When product identification information acquired by the wireless tag reader is different from currently displayed product identification information, the electronic shelf labels request a label change registration to a server. Changed product information is received according to the label change registration, and the changed product information is reflected in displayed product information.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including an active pattern protruding from a substrate; a plurality of gate structures each including a gate electrode and crossing the active pattern; and a source/drain region between the plurality of gate structures, wherein the source/drain region includes a high concentration doped layer in contact with a bottom surface of a recessed region in the active pattern, a first epitaxial layer in contact with an upper surface of the high concentration doped layer and a sidewall of the recessed region, and a second epitaxial layer on the first epitaxial layer, and the high concentration doped layer has a first area in contact with the bottom surface of the recessed region and a second area in contact with the sidewall of the recessed region, the first area being wider than the second area.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including an active pattern protruding from a substrate; a plurality of gate structures each including a gate electrode and crossing the active pattern; and a source/drain region between the plurality of gate structures, wherein the source/drain region includes a high concentration doped layer in contact with a bottom surface of a recessed region in the active pattern, a first epitaxial layer in contact with an upper surface of the high concentration doped layer and a sidewall of the recessed region, and a second epitaxial layer on the first epitaxial layer, and the high concentration doped layer has a first area in contact with the bottom surface of the recessed region and a second area in contact with the sidewall of the recessed region, the first area being wider than the second area.

Abstract: An pressure sensitive adhesive composition according to the present invention includes: an acrylic copolymer; a multifunctional acrylate-based compound; and a photoinitiator, in which the acrylic copolymer includes a repeating unit derived from an acrylate-based monomer having a Tg of ?20° C. or less and a repeating unit derived from an unsaturated carboxylic acid monomer, and the repeating unit derived from the unsaturated carboxylic acid monomer is included in an amount of 10 to 50 parts by weight based on the total 100 parts by weight of the acrylic copolymer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.