Patents by Inventor Jeong-Jik NA

Jeong-Jik NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit and memory
    Patent number: 11335398
    Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-down enable signal by delaying an input signal; and a second delay path configured to generate the pull-up enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeong-Jik Na
  • INTEGRATED CIRCUIT AND MEMORY
    Publication number: 20210050050
    Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-down enable signal by delaying an input signal; and a second delay path configured to generate the pull-up enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventor: Jeong-Jik NA
  • Integrated circuit and memory
    Patent number: 10872657
    Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-up enable signal by delaying an input signal; and a second delay path configured to generate the pull-down enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeong-Jik Na
  • INTEGRATED CIRCUIT AND MEMORY
    Publication number: 20200211624
    Abstract: An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-up enable signal by delaying an input signal; and a second delay path configured to generate the pull-down enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
    Type: Application
    Filed: December 13, 2019
    Publication date: July 2, 2020
    Inventor: Jeong-Jik NA