Abstract: Disclosed herein are methods and corresponding systems and devices for compensating burn-in in an electronic display. When the electronic display is divided into multiple regions, each region can have a separate compensation parameter associated with it. The compensation parameter can be determined through estimating pixel degradation based on how the region was used over the lifetime of the electronic display, for instance, the brightness of images previously displayed in the region. Although each region may have its own compensation parameter, burn-in compensation can be performed by selecting one compensation parameter from among a set of stored parameters for use as a global compensation parameter applied across all the display pixels, i.e., the entire display area. The global compensation parameter can be selected based on which region a user is looking at. Accordingly, a display system can include or be coupled to an eye-tracking unit that monitors eye movement.

Abstract: Embodiments relate to a pixel circuit of a display with a pixel level burn-in compensation. The pixel circuit includes a light-emitting diode (LED), a first driving transistor between a voltage source and the LED, an enable transistor coupled to a gate electrode of the first driving transistor, and a second driving transistor connected between the voltage source and the LED. The first driving transistor provides first current from the voltage source to the LED according to a gate voltage of the first driving transistor. The enable transistor turns on responsive to a voltage level at an anode of the LED increasing to a threshold voltage level. The second driving transistor provides second current from the voltage source to the LED according to a version of the gate voltage of the first driving transistor received at a gate electrode of the second driving transistor via the enable transistor.

Abstract: Embodiments of the present disclosure relate to a pixel circuit with a burn-in compensation. The pixel circuit includes a light-emitting diode (LED), a first driving transistor between a voltage source and the LED, a switching transistor coupled to a gate electrode of the first driving transistor, and a second driving transistor connected between the voltage source and the LED. The first driving transistor provides first current from the voltage source to the LED according to a gate voltage of the first driving transistor. The switching transistor is turned on after receiving an enable signal. The second driving transistor provides second current from the voltage source to the LED according to a version of the gate voltage of the first driving transistor received at a gate of the second driving transistor via the switching transistor.

Abstract: A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

Abstract: The present invention relates to a battery pack, and more particularly, to a battery pack configured to stably assemble a plurality of secondary batteries. Provided is a battery pack including a plurality of secondary batteries (100), a holder part (200) configured to fix the plurality of secondary batteries (100) so that the plurality of secondary batteries (100) constitute a unit module, and a conductive connection part that is in contact with the plurality of secondary batteries (100) to provide electrical connection with the outside. The holder part (200) are coupled to each of both ends of a positive electrode and a negative electrode of each of the plurality of secondary batteries (100).

Abstract: A comparator includes: a first selector for selecting one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel; a first comparator for comparing the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit for determining an output voltage at the current time of the target channel, based on the comparison result of the first comparator.

Abstract: A clock data recovery unit includes: a phase corrector generating a first compensation clock signal and a second compensation clock signal based on an external clock signal; and a transition detector, wherein the transition detector comprises: a first integrator configured to integrate a first training pattern signal according to the first compensation clock signal to provide a first integration signal; and a second integrator configured to integrate the first training pattern signal according to the second compensation clock signal to provide a second integration signal, wherein, in response to the first integration signal being greater than a first reference voltage and the second integration signal being less than the first reference voltage, occurrence of a transition of the first training pattern signal is detected.

Abstract: A clock data recovery unit includes: a phase corrector generating a first compensation clock signal and a second compensation clock signal based on an external clock signal; and a transition detector, wherein the transition detector comprises: a first integrator configured to integrate a first training pattern signal according to the first compensation clock signal to provide a first integration signal; and a second integrator configured to integrate the first training pattern signal according to the second compensation clock signal to provide a second integration signal, wherein, in response to the first integration signal being greater than a first reference voltage and the second integration signal being less than the first reference voltage, occurrence of a transition of the first training pattern signal is detected.

Abstract: A transition detector includes a first integrator configured to provide a first integral signal by integrating a first training pattern signal according to a first compensation clock signal, a second integrator configured to provide a second integral signal by integrating the first training pattern signal according to a second compensation clock signal, and a third integrator configured to provide a third integral signal by integrating the first training pattern signal according to a third compensation clock signal, wherein occurrence of a transition of the first training pattern signal is detected when the first integral signal and the second integral signal are larger than, and the third integral signal is smaller than, a first reference voltage.

Abstract: A receiver may include a plurality of receiving units connected with corresponding channels, and a clock data recovery unit connected with a sensing channel among the channels via a sensing line and connected with the receiving units via a common clock line. The receiving units may receive training pattern signals having the same transition direction through the channels in a training mode, and, in the training mode the clock data recovery unit may generate a phase-adjusted sampling clock signal so that a sampling time corresponds to a transition time of a training pattern signal of the sensing channel.

Abstract: A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

Abstract: A comparator includes: a first selector for selecting one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel; a first comparator for comparing the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit for determining an output voltage at the current time of the target channel, based on the comparison result of the first comparator.

Abstract: A transition detector includes a first integrator configured to provide a first integral signal by integrating a first training pattern signal according to a first compensation clock signal, a second integrator configured to provide a second integral signal by integrating the first training pattern signal according to a second compensation clock signal, and a third integrator configured to provide a third integral signal by integrating the first training pattern signal according to a third compensation clock signal, wherein occurrence of a transition of the first training pattern signal is detected when the first integral signal and the second integral signal are larger than, and the third integral signal is smaller than, a first reference voltage.

Abstract: Provided herein may be a receiver and a compensation method using the same. The receiver may be coupled to a transmitter through a plurality of channels, and may include a decoder configured to sample a received signal of a corresponding channel of the channels at a sampling point, and a controller configured to provide to the decoder a sampling clock signal for determining the sampling point, measure a level of the received signal having a transition direction that is identical to that of an adjacent received signal of an adjacent channel of the channels at the sampling point, during a compensation period, and adjust a phase of the sampling clock signal such that the measured level is at an intermediate level among variable levels of the received signal, during the compensation period.

Abstract: A receiver may include a plurality of receiving units connected with corresponding channels, and a clock data recovery unit connected with a sensing channel among the channels via a sensing line and connected with the receiving units via a common clock line. The receiving units may receive training pattern signals having the same transition direction through the channels in a training mode, and, in the training mode the clock data recovery unit may generate a phase-adjusted sampling clock signal so that a sampling time corresponds to a transition time of a training pattern signal of the sensing channel.

Abstract: Provided herein may be a receiver and a compensation method using the same. The receiver may be coupled to a transmitter through a plurality of channels, and may include a decoder configured to sample a received signal of a corresponding channel of the channels at a sampling point, and a controller configured to provide to the decoder a sampling clock signal for determining the sampling point, measure a level of the received signal having a transition direction that is identical to that of an adjacent received signal of an adjacent channel of the channels at the sampling point, during a compensation period, and adjust a phase of the sampling clock signal such that the measured level is at an intermediate level among variable levels of the received signal, during the compensation period.

Abstract: An organic light-emitting diode (OLED) display and method of driving the same are disclosed. In one aspect, the OLED display includes a display panel including a plurality of pixels and a data driver configured to apply a data signal to the display panel in one of two-dimensional (2D) and stereoscopic display modes. The display also includes a controller configured to convert an image signal to 2D image data for the pixels at each of N×k sub-fields in the 2D display mode and convert the image signal to stereoscopic image data for the pixels at each of N sub-fields in the stereoscopic display mode, where N and k are integers greater than 1. The display further includes a frame memory configured to store the 2D image data in the 2D display mode and the stereoscopic image data in the stereoscopic display mode.

Abstract: An organic light emitting display device includes a substrate including a display area on which a plurality of pixels are formed and a non-display area surrounding the display area; a first power line positioned on a lower non-display area; an auxiliary power line positioned on an upper non-display area; a first power supply supplying a first voltage to the first power line; and an auxiliary power supply supplying an auxiliary voltage to the auxiliary power line. Accordingly, it is possible to provide an organic light emitting display device capable of equalizing luminance by minimizing a variation in power supplied to each pixel.

Abstract: An organic light-emitting diode (OLED) display and method of driving the same are disclosed. In one aspect, the OLED display includes a display panel including a plurality of pixels and a data driver configured to apply a data signal to the display panel in one of two-dimensional (2D) and stereoscopic display modes. The display also includes a controller configured to convert an image signal to 2D image data for the pixels at each of N×k sub-fields in the 2D display mode and convert the image signal to stereoscopic image data for the pixels at each of N sub-fields in the stereoscopic display mode, where N and k are integers greater than 1. The display further includes a frame memory configured to store the 2D image data in the 2D display mode and the stereoscopic image data in the stereoscopic display mode.

Abstract: A scan driving unit and OLED display device including the unit are disclosed. In one aspect, the unit includes a first pre-decoder block that receives upper scan-line selection signals for selecting one of upper scan-lines that are arranged in an upper display region of a display panel, and outputs first logic signals based on the upper scan-line selection signals. It also includes a second pre-decoder block that receives lower scan-line selection signals for selecting one of lower scan-lines that are arranged in a lower display region of the display panel, and outputs second logic signals based on the lower scan-line selection signals. It further includes a first final-decoder block coupled between the upper display region and the first pre-decoder block that selects one of the upper scan-lines based on the first logic signals, and a second final-decoder block coupled between the lower display region and the second pre-decoder block that selects one of the lower scan-lines based on the second logic signals.