Abstract: Disclosed is a continuous time linear equalizer circuit having a higher bandwidth by a plurality of filters connected to different signal paths in a T-coil circuit.

Abstract: A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.

Abstract: A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing s

Abstract: A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.

Abstract: A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing s

Abstract: A receiving circuit may include a decision feedback equalizer circuit and buffer. The buffer may be configured to receive an external signal and to generate an input signal. The decision feedback equalizer circuit may include a plurality of delay circuits, and may be configured to generate an internal signal based on the input signal, a strobe signal, and outputs of the plurality of delay circuits. The plurality of delay circuits may be reset based on whether or not the strobe signal has toggled or not between command signals.

Abstract: A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

Abstract: A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

Abstract: A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.

Abstract: A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

Abstract: A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength.

Abstract: A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

Abstract: An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Abstract: A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

Abstract: A stacked die package includes a package substrate, a first die mounted on the package substrate and electrically connected to the package substrate, a second die electrically connected to the package substrate, and an interposer mounted on the package substrate and including a plurality of vertical electrical connection means electrically connecting the package substrate to the second die. At least part of the first die is disposed between the second die and the package substrate in a vertical direction.

Abstract: A memory system includes a memory controller and a memory device. The memory device includes a first converter and a first power controller. The memory device is connected to the memory controller through a channel including at least one optical signal line. The first converter converts between at least one optical signal of the at least one optical signal line and at least one internal electrical signal of the memory device. The first power controller controls power consumption of the first converter based on an operating state of the memory device.

Abstract: An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Abstract: A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength.

Abstract: An electro-photonic memory system includes a semiconductor memory device for storing data by receiving a first electrical signal, a memory controller for generating a second electrical signal to control the semiconductor memory device, an electrical-to-optical converter for receiving the second electrical signal from the memory controller and converting the second electrical signal into an optical signal, the electrical-to-optical converter separate from the memory controller, and an optical-to-electrical converter for receiving the optical signal from the electrical-to-optical converter and converting the optical signal into the first electrical signal.

Abstract: A stacked die package includes a package substrate, a first die mounted on the package substrate and electrically connected to the package substrate, a second die electrically connected to the package substrate, and an interposer mounted on the package substrate and including a plurality of vertical electrical connection means electrically connecting the package substrate to the second die. At least part of the first die is disposed between the second die and the package substrate in a vertical direction.