Abstract: A method according to an embodiment is for recovering a valuable metal from a waste electrode material of a lithium secondary battery by using lithium carbonate. An anode-cathode mixed electrode material that has been separated by draining, crushing, screening, and sorting a waste lithium secondary battery is preprocessed. A precipitation operation performed by adding lithium carbonate (Li2CO3) to a metal melt acquired by performing sulfuric acid dissolution using sulfuric acid. A valuable metal such as nickel, cobalt, manganese, aluminum, and copper is recovered as a residue in the form of a carbonate composite, and a lithium sulfate (Li2SO4) aqueous solution including lithium is recovered as a filtrate.

Abstract: A method and an apparatus for acquiring a signal of a global navigation satellite system (GNSS) are provided. The method includes: performing a first satellite signal acquiring operation based on an initially set Doppler frequency search start value and an initially set Doppler frequency search interval value; and changing the initially set Doppler frequency search start value and performing a second satellite signal acquiring operation when a satellite signal is not found through the first satellite signal acquiring operation.

Abstract: The present invention relates to an analysis method for the mi-RNA ID. More specifically, the invention relates to improve the analysis capabilities of the mi-RNA and to a method of analysis mi-RNA ID anticipating the generation of the cancer cells through this. In addition, the present invention is to apply to the biomarkers of colon cancer obtained by the mi-RNA ID analysis result gained through the analysis of the mi-RNA ID.

Abstract: A method and an apparatus for acquiring a signal of a global navigation satellite system (GNSS) are provided. The method includes: performing a first satellite signal acquiring operation based on an initially set Doppler frequency search start value and an initially set Doppler frequency search interval value; and changing the initially set Doppler frequency search start value and performing a second satellite signal acquiring operation when a satellite signal is not found through the first satellite signal acquiring operation.

Abstract: Example embodiments are directed to a method for detection and avoidance (DAA) of an ultra wide band (UWB) signal and a UWB terminal. The method includes: shifting a data signal by a desired frequency in a first direction; filtering the shifted data signal through a notch filter; and shifting the filtered data signal by the desired frequency in a second direction, the second direction being opposite to the first direction. The UWB terminal comprises an encoder for encoding data signals; a tone nulling unit for changing at least one tone of the plurality of tones into a null tone; an inverted fast Fourier transformer; a low pass filter for filtering the inverted fast Fourier transformed data signals; a filter circuit for attenuating an intensity of the low pass filtered signal; and a radio frequency (RF) circuit for transmitting the filtered signal.

Abstract: A bit interleaver and a bit interleaving method are provided. The bit interleaver includes delay devices which are applied with symbol interleaving and tone interleaving, and delay a bit stream output from a memory, to generate a delayed bit stream; a first multiplexer (MUX) unit which selects any one of a bit of the bit stream output from the memory and a bit of the delayed bit stream, to generate a selection bit stream; and a second MUX unit which changes an order of the selection bit stream to generate an output bit stream. Accordingly, it is possible to easily and effectively perform bit interleaving including a cyclic shift.

Abstract: Provided is an interleaving method that can reduce error occurring during transmission at a receiving end in an Orthogonal Frequency Division Multiplexing (OFDM) system. According to the interleaving method, transmitted data bits are recorded in an interleaving memory; and the stored data bits are read based on a predetermined sequence to perform symbol interleaving, tone interleaving and cyclic shift simultaneously. Also, to simplify the logic of the OFDM system, the data bits transmitted from an interleaver go through Fast Fourier Transform (FFT) mapping, and the FFT mapped data bits are modulated. In short, the logic can be simplified by performing FFT mapping followed by modulation.

Abstract: An FFT apparatus for quickly processing input signals and method thereof is disclosed. In performing the FFT for processing N input signals, four N/4-point FFT units implemented by radix-2 single-path delay feedback (R2SDF) units performs the FFT with respect to the input signals, and a radix-4 computation unit performs a radix-4 computation with respect to the signals transferred from the N/4-point FFT units. Accordingly, the input signals are processed in parallel through the N/4-point FFT units, and thus a quick process of the input signals can be performed.

Abstract: An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are sequentially calculated according to a predetermined process, and reading data stored at read address values of the memory which are sequentially calculated according to a predetermined process, wherein the memory has N data banks, each data bank has M storage spaces, and there are D interleaving target data having data numbers A, and the storing data operation includes storing the data at storage spaces of the data banks, the storage spaces corresponding to integer values and the data banks corresponding to remainders obtained by dividing the data numbers A by results of dividing a total number of data D by the number of storage spaces M.

Abstract: Example embodiments are directed to a method for detection and avoidance (DAA) of an ultra wide band (UWB) signal and a UWB terminal. The method includes: shifting a data signal by a desired frequency in a first direction; filtering the shifted data signal through a notch filter; and shifting the filtered data signal by the desired frequency in a second direction, the second direction being opposite to the first direction. The UWB terminal comprises an encoder for encoding data signals; a tone nulling unit for changing at least one tone of the plurality of tones into a null tone; an inverted fast Fourier transformer; a low pass filter for filtering the inverted fast Fourier transformed data signals; a filter circuit for attenuating an intensity of the low pass filtered signal; and a radio frequency (RF) circuit for transmitting the filtered signal.

Abstract: Disclosed is a European digital audio broadcast receiver having a simply implementable fast Fourier transform processor and an operation method therefor. A digital audio broadcast receiver having diverse fast Fourier transform (FFT) modes based on sizes of transmitted data has an address generator for generating a predetermined number of write addresses and read addresses, a fast Fourier transform (FFT) processor for repeating data of FFT modes to generate a predetermined number of data and implementing a fast Fourier transform (FFT) by using the predetermined number of data, and a controller for controlling the address generator to the write addresses and the read addresses according to operations of the FFT processor.

Abstract: A DAA method of a UWB signal with respect to a WiMax signal, the method including: generating the UWB signal by tone mapping a predetermined data bit; and controlling a first band to shift to a second band where an interference with the WiMax signal occurs, the first band including a null tone among mapped tones of the UWB signal.

Abstract: A bit interleaver and a bit interleaving method are provided. The bit interleaver includes delay devices which are applied with symbol interleaving and tone interleaving, and delay a bit stream output from a memory, to generate a delayed bit stream; a first multiplexer (MUX) unit which selects any one of a bit of the bit stream output from the memory and a bit of the delayed bit stream, to generate a selection bit stream; and a second MUX unit which changes an order of the selection bit stream to generate an output bit stream. Accordingly, it is possible to easily and effectively perform bit interleaving including a cyclic shift.

Abstract: Disclosed are a Viterbi decoding method and apparatus for high speed data transmissions. Branch metric is used with data inputted from a Viterbi decoder used in a communication system, and, when current state metric is used for addition, comparison, and selection, the selection operation is performed after simultaneous addition and comparison operations are performed, so that a faster decoding processing speed is obtained. The decoding process is carried out at a high speed with the addition and comparison operations carried out simultaneously, thereby preventing the increase of power consumption.

Abstract: An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are sequentially calculated according to a predetermined process, and reading data stored at read address values of the memory which are sequentially calculated according to a predetermined process, wherein the memory has N data banks, each data bank has M storage spaces, and there are D interleaving target data having data numbers A, and the storing data operation includes storing the data at storage spaces of the data banks, the storage spaces corresponding to integer values and the data banks corresponding to remainders obtained by dividing the data numbers A by results of dividing a total number of data D by the number of storage spaces M.

Abstract: A Fast Fourier Transforming apparatus and method thereof for compensating for an OFDM output bit signal is described. The apparatus includes an input buffer unit for storing and outputting a received OFDM bit signal and a butterfly operation unit for performing a butterfly operation according to a radix algorithm. The apparatus comprises a scale detection unit for calculating and outputting a scale factor which is a division factor used for controlling a bit value of a butterfly operated signal input from the butterfly operation unit at each of the stages to a predetermined bit limit of the received OFDM signal, a scale count unit for cumulative counting a count figures corresponding to the scale factor input from the scale detection unit and outputting the result, and a compensation unit for controlling the bit of a signal input from the butterfly operation unit according to result values from the scale detection unit and the scale count unit and outputting the result.

Abstract: A dual carrier modulator that modulates an orthogonal frequency division multiplexing (OFDM) carrier, includes an input part receiving a predetermined number of coded bits; a memory part storing the coded bits received through the input part; a detection part detecting four bits among the coded bits in a predetermined order; and an operation part generating a modulated symbol comprising a real part and an imaginary part, using the four detected bits and a predetermined unitary matrix. Here, one of the detected four bits is included in a real part of a first modulated symbol and in an imaginary part of a second modulated symbol. Accordingly, loss of signals caused by mismatching between an In-phase channel and a Quadrature channel can be prevented.

Abstract: Provided is an interleaving method that can reduce error occurring during transmission at a receiving end in an Orthogonal Frequency Division Multiplexing (OFDM) system. According to the interleaving method, transmitted data bits are recorded in an interleaving memory; and the stored data bits are read based on a predetermined sequence to perform symbol interleaving, tone interleaving and cyclic shift simultaneously. Also, to simplify the logic of the OFDM system, the data bits transmitted from an interleaver go through Fast Fourier Transform (FFT) mapping, and the FFT mapped data bits are modulated. In short, the logic can be simplified by performing FFT mapping followed by modulation.

Abstract: An FFT apparatus for quickly processing input signals and method thereof is disclosed. In performing the FFT for processing N input signals, four N/4-point FFT units implemented by radix-2 single-path delay feedback (R2SDF) units performs the FFT with respect to the input signals, and a radix-4 computation unit performs a radix-4 computation with respect to the signals transferred from the N/4-point FFT units. Accordingly, the input signals are processed in parallel through the N/4-point FFT units, and thus a quick process of the input signals can be performed.

Abstract: Disclosed is fast Fourier transform device and method for improving a processing speed. The fast Fourier transform device includes a memory part having N memory addresses at which the N data items are written, and having a structure dividing the memory addresses into even-numbered addresses and odd-numbered addresses. An address generation unit generates addresses each including bits except for the most significant bit with respect to the memory addresses. A computation part reads the data items at the even-numbered addresses and odd-numbered addresses based on the addresses generated in the address generation unit, and performing Radix-2 based butterfly computations. The fast Fourier transform device arranges the messed-up memory addresses in order in a new digit-reverse manner. Accordingly, the fast Fourier transform device operates the two butterfly computation structures at the same time so as to reduce the processing time by half as well as to simplify the implementation thereof.