Abstract: An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency.

Abstract: A cache memory system includes a cache memory, which stores cache data corresponding to portions of main data stored in a main memory and priority data respectively corresponding to the cache data; a table storage unit, which stores a priority table including information regarding access frequencies with respect to the main data; and a controller, which, when at least one from among the main data is requested, determines whether cache data corresponding to the request is stored in the cache memory, deletes one from among the cache data based on the priority data, and updates the cache data set with new data, wherein the priority data is determined based on the information regarding access frequencies.

Abstract: Provided is an image processing apparatus. The image processing apparatus may perform an intersection test for rendering of a ray tracing scheme. The image processing apparatus may include a first calculator and a second calculator. The first calculator may perform a ray-plane test to determine whether a ray intersects a plane including a primitive and a barycentric test to determine whether the ray intersects the primitive. The second calculator may calculate a hit point based on the ray which intersects the primitive.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract: An apparatus and method for processing a primitive in a three-dimensional (3D) graphics rendering system is provided. The primitive processing apparatus may discard a primitive or store the primitive in a memory, depending on whether a sampling point overlapping the primitive is present among sampling points in a pixel area.

Abstract: A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.

Abstract: A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract: A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced.

Abstract: An image rendering apparatus may include a buffer memory unit and a processor. The buffer memory unit may store input ray data for image rendering according to a ray tracing scheme while shape data corresponding to the input ray data is being fetched from a cache. The processor may output the received shape data together with the input ray data to an operation apparatus.

Abstract: Provided is an image processing apparatus. The image processing apparatus may perform an intersection test for rendering of a ray tracing scheme. The image processing apparatus may include a first calculator and a second calculator. The first calculator may perform a ray-plane test to determine whether a ray intersects a plane including a primitive and a barycentric test to determine whether the ray intersects the primitive. The second calculator may calculate a hit point based on the ray which intersects the primitive.

Abstract: An image processing apparatus is provided. A splitting unit of the image processing apparatus may split a first space within an input three-dimensional (3D) model into a plurality of subspaces in order to generate an acceleration structure of the input 3D model. A decision unit of the image processing apparatus may set a subspace determined as having a relatively high probability of including a ray progress path among the plurality of subspaces, as a child node having a relatively high traversal priority in the acceleration structure among a plurality of child nodes.

Abstract: A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced.

Abstract: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract: A rendering apparatus and method are provided. The rendering method includes: reading a block, corresponding to a fragment, from among compressed blocks stored in a depth buffer, by considering frequency information corresponding to the fragment and prepared in advance; and performing a depth test for the fragment by considering the restored block.

Abstract: The present invention relates to nucleic acid sequences and proteins involved in senescence and particularly, to nucleic acid sequences and proteins including amphiphysin and caveolin involved in cellular senescence and their use.

Abstract: The present invention relates to nucleic acid sequences and proteins involved in senescence and particularly, to nucleic acid sequences and proteins including amphiphysin and caveolin involved in cellular senescence and their use.

Abstract: A method of fabricating semiconductor device is provided that includes a method of forming plugs in a semiconductor device. The plugs or contacts can connect an upper conductive layer to a lower conductive layer. The plugs are preferably formed without providing contact holes. The method of fabricating a semiconductor device can include the steps of defining an active area of a device by forming a field insulating layer on a semiconductor substrate of a first conductivity type, forming a gate oxide on an exposed surface of the active layer and forming a plurality of gates and associated cap insulating layers along a first direction perpendicular to an active area. An impurity region of a second conductivity type is formed in the exposed active area of the semiconductor substrate and a plurality of sidewall spacers are formed at sides of the gates. An electrically-conductive layer is formed for contacting the impurity region between the gates on the semiconductor substrate.

Abstract: A dual gate MOSFET fabrication method includes the steps of forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer, forming a first photoresist pattern on the first polysilicon layer, forming a first gate by sequentially etching the first polysilicon layer and the first insulation layer by using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second insulation layer on the semiconductor substrate and the first gate, forming a second polysilicon layer on the second insulation layer, forming a second photoresist pattern on the second polysilicon layer, and forming a second gate by etching the second polysilicon layer and the second insulation layer by using the second photoresist pattern as a mask.