Abstract: Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: Integrated circuit devices include a pair of field effect transistors having shared source terminals, shared drain terminals and shared gate terminals, which may be treated herein as being electrically coupled in parallel. A switch circuit is also provided, which is configured to drive a body terminal of a first one of the pair of field effect transistors with an alternating sequence of first and second unequal body voltages. This alternating sequence is synchronized with a first clock signal. The switch circuit is also configured to drive a body terminal of a second one of the pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages, which is synchronized with a second clock signal. The first and third body voltages may have equivalent magnitudes and the second and fourth body voltages may have equivalent magnitudes. The first and second clock signals may have 50% duty cycles and may be 180 degrees out-of-phase relative to each other.

Abstract: Provided is a complementary metal oxide semiconductor variable gain amplifier controlling a dB linear gain and a method of controlling the dB linear gain. The complimentary metal oxide semiconductor variable gain amplifier includes: first through fourth transistors differentially receiving first and second input voltages and amplifying the first and second input voltage using a predetermined gain; fifth and sixth transistors controlling a transconductance according to a control voltage to control the predetermined gain; and first and second resistors generating an output voltage having the predetermined gain according to an output current generated by the fifth and sixth transistors.

Abstract: The differential amplifier and an active load are provided. The differential amplifier includes a differential input section which is configured to generate a differential current according to a differential input signal; and an active load which is configured to generate a differential output signal according to the differential current. The active load includes first and second active load sections comprising a first negative feedback loop and a second negative feedback loop, respectively; and a common mode feedback section comprising a feedback current source which supplies a feedback current to the first active load section and the second active load section to form a common mode feedback path.

Abstract: Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: The differential amplifier and an active load are provided. The differential amplifier includes a differential input section which is configured to generate a differential current according to a differential input signal; and an active load which is configured to generate a differential output signal according to the differential current. The active load includes first and second active load sections comprising a first negative feedback loop and a second negative feedback loop, respectively; and a common mode feedback section comprising a feedback current source which supplies a feedback current to the first active load section and the second active load section to form a common mode feedback path.

Abstract: A stacked CMOS current mirror using metal oxide semiconductor field effect transistors (MOSFETs) having different threshold voltages is disclosed. The stacked CMOS current mirror includes a first MOSFET having a source and a gate which are connected to a first input current terminal, a second MOSFET having a source connected to a drain of the first MOSFET, a gate connected to the gate of the first MOSFET, and a drain connected to ground, a third MOSFET having a drain connected to a second input current terminal and a gate connected to the source and the gate of the first MOSFET, and a fourth MOSFET having a drain connected to a source of the third MOSFET, a gate connected to the source and the gate of the first MOSFET, and a source connected to the ground.

Abstract: Provided is a complementary metal oxide semiconductor variable gain amplifier controlling a dB linear gain and a method of controlling the dB linear gain. The complimentary metal oxide semiconductor variable gain amplifier includes: first through fourth transistors differentially receiving first and second input voltages and amplifying the first and second input voltage using a predetermined gain; fifth and sixth transistors controlling a transconductance according to a control voltage to control the predetermined gain; and first and second resistors generating an output voltage having the predetermined gain according to an output current generated by the fifth and sixth transistors.

Abstract: An exponential function generator for generating an exponential generator to realize a linear region of about 60 dB required for the an ultra wide band system (UWB). Since the exponential function generator is implemented in a form of complementary metal oxide semiconductor fabrication (CMOS), compactness and operation control of the exponential function generator can be facilitated.