Patents by Inventor Jeong-yeop Lee

Jeong-yeop Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147763
    Abstract: A thin film transistor array substrate includes a substrate including an active area and a non-active area, a first thin film transistor disposed on the substrate, and a first light shielding pattern between the substrate and the first thin film transistor, the first thin film transistor includes a first oxide semiconductor pattern disposed on the substrate, a first gate electrode, a first gate insulating layer interposed between the first oxide semiconductor pattern and the first gate electrode, a first source electrode, and a first drain electrode, the first light shielding pattern electrically connected to one of the first source electrode and the first drain electrode is disposed under the first oxide semiconductor pattern, and the first oxide semiconductor pattern includes a first portion configured to form a first parasitic capacitance, together with the first gate electrode, and a second portion configured to form a second parasitic capacitance different from the first parasitic capacitance, together w
    Type: Application
    Filed: September 14, 2023
    Publication date: May 2, 2024
    Applicant: LG Display Co., Ltd.
    Inventor: Jeong Yeop LEE
  • Publication number: 20230061983
    Abstract: A display apparatus may include at least one switching thin film transistor and a driving thin film transistor, which are disposed on a device substrate. The driving thin film transistor may include a driving semiconductor pattern made of an oxide semiconductor. A light-blocking pattern may be disposed between the device substrate and the driving semiconductor pattern. The light-blocking pattern may be disposed close to the driving semiconductor pattern. Thus, in the display apparatus, a current variation value according to a voltage applied to the driving gate electrode of the driving thin film transistor may be reduced, without changing the characteristics of the switching thin film transistor. Thereby, in the display apparatus, the occurrence of a spot in low grayscale may be prevented.
    Type: Application
    Filed: August 10, 2022
    Publication date: March 2, 2023
    Applicant: LG Display Co., Ltd.
    Inventors: Duk Young JEONG, Ki Sul CHO, Jeong Yeop LEE, Jang Dae KIM, Min Cheol KIM
  • Publication number: 20220359643
    Abstract: Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
    Type: Application
    Filed: November 2, 2021
    Publication date: November 10, 2022
    Inventors: Kwan Woo DO, Wan Joo MAENG, Jeong Yeop LEE, Ki Vin IM
  • Patent number: 11322501
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 11217592
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 10879833
    Abstract: A blower register includes a movable terminal, a plurality of fixed terminals to which the movable terminal is selectively connected, a plurality of resistors installed on the downstream side of the fixed terminals to adjust a current value of an electric current applied to a blower, and a current flow control part configured to subdivide the current value of the electric current in a number larger than the number of the fixed terminals and to form current flow paths through the resistors so that a rotation speed level of the blower is controlled to one of rotation speed levels larger in number than the fixed terminals.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: December 29, 2020
    Assignee: Hanon Systems
    Inventor: Jeong Yeop Lee
  • Publication number: 20200335505
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10734389
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20200152637
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10580777
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20200043933
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 6, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10483265
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20190131306
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Publication number: 20190115864
    Abstract: A blower register includes a movable terminal, a plurality of fixed terminals to which the movable terminal is selectively connected, a plurality of resistors installed on the downstream side of the fixed terminals to adjust a current value of an electric current applied to a blower, and a current flow control part configured to subdivide the current value of the electric current in a number larger than the number of the fixed terminals and to form current flow paths through the resistors so that a rotation speed level of the blower is controlled to one of rotation speed levels larger in number than the fixed terminals.
    Type: Application
    Filed: March 22, 2018
    Publication date: April 18, 2019
    Inventor: Jeong Yeop LEE
  • Publication number: 20180301457
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: January 9, 2018
    Publication date: October 18, 2018
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE
  • Patent number: 9828402
    Abstract: A film-forming composition including a 3-intracyclic cyclopentadienyl precursor and dimethyethylamine is useful for Atomic Layer Deposition, and improves viscosity and volatility while maintaining unique features of metal precursors.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: November 28, 2017
    Assignees: SK Hynix Inc., SOULBRAIN SIGMA-ALDRICH, LTD
    Inventors: Ji-Won Moon, Young-Jin Son, Jeong-Yeop Lee, Jun-Soo Jang, Jae-Sun Jung, Sang-Kyung Lee, Chang-Sung Hong, Hyun-Joon Kim, Jin-Ho Shin, Dae-Hyun Kim
  • Publication number: 20160273103
    Abstract: A film-forming composition including a 3-intracyclic cyclopentadienyl precursor and dimethyethylamine is useful for Atomic Layer Deposition, and improves viscosity and volatility while maintaining unique features of metal precursors.
    Type: Application
    Filed: September 16, 2015
    Publication date: September 22, 2016
    Inventors: Ji-Won MOON, Young-Jin SON, Jeong-Yeop LEE, Jun-Soo JANG, Jae-Sun JUNG, Sang-Kyung LEE, Chang-Sung HONG, Hyun-Joon KIM, Jin-Ho SHIN, Dae-Hyun KIM
  • Patent number: 8786792
    Abstract: A mother substrate for a liquid crystal display device includes: a substrate; a plurality of unit array patterns on the substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; a first electrostatic discharge pattern surrounding the plurality of unit array patterns; a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; and a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern contacting the second electrostatic discharge pattern.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: July 22, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jeong-yeop Lee, Jae-myung Seok, Jae-woo Jung, Young-seok Choi, Hyock-jae Shin
  • Patent number: 8728887
    Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor
    Inventors: Jeong-Yeop Lee, Hyung-Soon Park, Young-Bang Lee, Su-Young Kim
  • Publication number: 20130164903
    Abstract: A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.
    Type: Application
    Filed: May 10, 2012
    Publication date: June 27, 2013
    Inventors: Jeong-Yeop Lee, Hyung-Soon Park, Young-Bang Lee, Su-Young Kim