Abstract: A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated.

Abstract: A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated.

Abstract: An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.

Abstract: Circuits and methods are described for reducing leakage power in integrated circuit devices whose logic transistors (e.g., logic circuits, latches, and/or output stages) are powered through one or more controllable source transistors. By way of example the circuit has at least one source transistor (e.g., power, ground, or both power and ground) for selectively supplying power to a stage within an integrated circuit device. A means for modulating the state of the source transistor operates in response to changes in the operating mode of the integrated circuit to turn on the source transistor prior to turning on the logic transistors, and/or to turn off the source transistor after turning off the logic transistors. In one aspect, the delay prior to turning off the logic transistors can be sufficiently extended to reduce power consumption arising from unnecessarily turning on and off the source transistors for short periods.

Abstract: An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.

Abstract: An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.

Abstract: Memory circuits and methods are described providing an interface with high density dynamic memory (DRAM), such 1T1C (1 transistor and 1 capacitor) memory cells, providing full compatibility with static memory (SRAM). The circuitry overcomes the shortcomings with DRAM, such as associated with the restore and refresh operations, which have prevented full utilization of DRAM cores with SRAM compatible devices. The circuit can incorporate a number of inventive aspects, either singly or more preferably in combination, including a pulsed word line structure for limiting the maximum page mode cycle time, an address duration compare function with optional address buffering, and a late write function wherein the write operation commences after the write control signals are disabled.

Abstract: Memory circuits and methods are described providing an interface with high density dynamic memory (DRAM), such 1T1C (1 transistor and 1 capacitor) memory cells, providing full compatibility with static memory (SRAM). The circuitry overcomes the shortcomings with DRAM, such as associated with the restore and refresh operations, which have prevented full utilization of DRAM cores with SRAM compatible devices. The circuit can incorporate a number of inventive aspects, either singly or more preferably in combination, including a pulsed word line structure for limiting the maximum page mode cycle time, an address duration compare function with optional address buffering, and a late write function wherein the write operation commences after the write control signals are disabled.

Abstract: An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.