Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.

Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AH traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.

Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AR traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.

Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AH traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.