Patents by Inventor Jer-Chyi Wang
Jer-Chyi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11653903Abstract: The invention relates to an automatic reflection hammer system, which comprises the following components: a reflective hammer chassis, an outer side having a detachable reflection hammer head, and a pulley, a universal joint, a vertical height adjustment mechanism, and a fixing bracket. Wherein, the reflection hammer chassis links with the universal joint, the universal joint links to the vertical height adjustment mechanism, and the vertical height adjustment mechanism links with the fixing bracket.Type: GrantFiled: September 10, 2019Date of Patent: May 23, 2023Assignee: CHANG GUNG UNIVERSITYInventors: Jer-Chyi Wang, Yi Fu, Kuo-Hsuan Chang
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Publication number: 20200178942Abstract: The invention relates to an automatic reflection hammer system, which comprises the following components: a reflective hammer chassis, an outer side having a detachable reflection hammer head, and a pulley, a universal joint, a vertical height adjustment mechanism, and a fixing bracket. Wherein, the reflection hammer chassis links with the universal joint, the universal joint links to the vertical height adjustment mechanism, and the vertical height adjustment mechanism links with the fixing bracket.Type: ApplicationFiled: September 10, 2019Publication date: June 11, 2020Inventors: Jer-Chyi WANG, Yi FU, Kuo-Hsuan CHANG
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Publication number: 20190148540Abstract: A floating gate non-volatile memory device includes at least one floating gate non-volatile memory cell including a semiconductor substrate, a gate stack unit, and a drain and source unit. The gate stack unit includes a tunnel oxide layer having a negative capacitance, a floating gate layer disposed on the tunnel oxide layer, a blocking oxide layer disposed on the floating gate layer and opposite to the tunnel oxide layer, and a control gate layer disposed on the blocking oxide layer and opposite to the floating gate layer. The drain and source unit is disposed in the semiconductor substrate and includes source and drain regions that are respectively disposed on two opposite sides of the gate stack unit.Type: ApplicationFiled: November 13, 2018Publication date: May 16, 2019Applicant: CHANG GUNG UNIVERSITYInventors: Jer-Chyi Wang, Yu-Hua Liu
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Patent number: 9105505Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.Type: GrantFiled: September 12, 2013Date of Patent: August 11, 2015Assignee: INOTERA MEMORIES, INC.Inventors: Chien-Chi Lee, Chia-Ming Yang, Wei-Ping Lee, Hsin-Huei Chen, Chih-Yuan Hsiao, Ping Kao, Kai-Lun Chiang, Chao-Sung Lai, Jer-Chyi Wang
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Publication number: 20140312401Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.Type: ApplicationFiled: September 12, 2013Publication date: October 23, 2014Applicant: INOTERA MEMORIES, INC.Inventors: Chien-Chi Lee, Chia-Ming Yang, Wei-Ping Lee, Hsin-Huei Chen, Chih-Yuan Hsiao, Ping Kao, Kai-Lun Chiang, Chao-Sung Lai, Jer-Chyi Wang
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Patent number: 8343829Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.Type: GrantFiled: June 28, 2011Date of Patent: January 1, 2013Assignee: Nanya Technology Corp.Inventors: Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee, Jeng-Ping Lin
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Publication number: 20110256697Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.Type: ApplicationFiled: June 28, 2011Publication date: October 20, 2011Inventors: Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee, Jeng-Ping Lin
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Patent number: 7994559Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.Type: GrantFiled: July 2, 2008Date of Patent: August 9, 2011Assignee: Nanya Technology Corp.Inventors: Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee, Jeng-Ping Lin
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Patent number: 7956403Abstract: A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.Type: GrantFiled: April 8, 2008Date of Patent: June 7, 2011Assignee: Nanya Technology CorporationInventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Yi-Feng Chang
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Patent number: 7667262Abstract: A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.Type: GrantFiled: June 15, 2008Date of Patent: February 23, 2010Assignee: Nanya Technology Corp.Inventors: Wei-Ming Liao, Jer-Chyi Wang
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Publication number: 20090267126Abstract: A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion situated in the round lower portion; a gate oxide layer in the round lower portion between the semiconductor substrate and the spherical gate portion; a source region in the active area at one side of the recessed gate; a drain region in the active area at the other side of the recessed gate; and a channel region between the source region and the drain region, wherein the channel region presents a convex curve profile when viewed from a channel widthwise direction.Type: ApplicationFiled: June 17, 2008Publication date: October 29, 2009Inventors: Jer-Chyi Wang, Wei-Ming Liao
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Publication number: 20090256189Abstract: A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.Type: ApplicationFiled: June 15, 2008Publication date: October 15, 2009Inventors: Wei-Ming Liao, Jer-Chyi Wang
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Publication number: 20090114968Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.Type: ApplicationFiled: July 2, 2008Publication date: May 7, 2009Inventors: Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee, Jeng-Ping Lin
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Publication number: 20090108321Abstract: A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate.Type: ApplicationFiled: November 30, 2007Publication date: April 30, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Chien-Chang Huang
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Publication number: 20090090955Abstract: A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density.Type: ApplicationFiled: March 28, 2008Publication date: April 9, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Jer-Chyi Wang, Ming-Cheng Chang, Yi-Feng Chang, Wei-Ming Liao, Chien-Chang Huang
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Publication number: 20090085089Abstract: A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.Type: ApplicationFiled: April 8, 2008Publication date: April 2, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Yi-Feng Chang
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Publication number: 20090020801Abstract: A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P+ source/drain region next to the spacer, and an N+ pocket region encompassing the P+ source/drain region and covering the area directly under the floating gate.Type: ApplicationFiled: December 6, 2007Publication date: January 22, 2009Inventors: Wei-Ming Liao, Ming-Cheng Chang, Jer-Chyi Wang
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Publication number: 20090017604Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate.Type: ApplicationFiled: November 1, 2007Publication date: January 15, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Mao-Ying WANG, Jer-Chyi WANG, Wei-Hui HSU, Liang-Pin CHOU, Kuo-Hui SU, Chang-Rong WU, Chao-Sung LAI
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Publication number: 20080283904Abstract: A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate.Type: ApplicationFiled: July 25, 2007Publication date: November 20, 2008Inventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Chien-Chang Huang
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Publication number: 20080265342Abstract: A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate.Type: ApplicationFiled: July 20, 2007Publication date: October 30, 2008Inventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Chien-Chang Huang