Patents by Inventor Jeremiah D. Burke

Jeremiah D. Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes
    Patent number: 6195676
    Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
    Type: Grant
    Filed: January 11, 1993
    Date of Patent: February 27, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli
  • System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling
    Patent number: 5179702
    Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: January 12, 1993
    Assignee: Supercomputer Systems Limited Partnership
    Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli