Patents by Inventor Jeremias P. Libres
Jeremias P. Libres has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7550856Abstract: A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a plurality of metallic terminal pads (306) in locations matching the locations of the device contact pads, and further a plurality of grooves (310) and humps (311) distributed between the terminal pad locations, complementing the distribution of the terminal pads. Each bump is further attached to its matching terminal pad, respectively; the device is thus interconnected with the substrate and spaced apart by a gap (320). Adherent polymeric material (330) containing inorganic fillers fills the gap substantially without voids.Type: GrantFiled: March 1, 2006Date of Patent: June 23, 2009Assignee: Texas Instruments IncorporatedInventors: Jeremias P. Libres, Joel T. Medina, Mary C. Miller
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Patent number: 7309648Abstract: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body attached. A semiconductor chip is positioned in the opening while leaving a gap to the substrate; the chip has an active surface including at least one bond pad, and a passive surface substantially coplanar with the second substrate surface. Substrate thickness and chip thickness may be substantially equal. Bonding elements bridge the gap to connect electrically bond pad and routing strip.Type: GrantFiled: September 6, 2006Date of Patent: December 18, 2007Assignee: Texas Instruments IncorporatedInventors: Navinchandra Kalidas, Jeremias P Libres, Michael P Pierce
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Patent number: 7135781Abstract: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate (301) with first and second surfaces (301a, 301b), at least one opening (310), and a certain thickness (302). On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads (330); at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body (901) attached. A semiconductor chip (102) is positioned in the opening while leaving a gap (311) to the substrate; the chip has an active surface (102a) including at least one bond pad (103), and a passive surface (102b) substantially coplanar with the second substrate surface (301b). Substrate thickness and chip thickness may be substantially equal. Bonding elements (501) bridge the gap to connect electrically bond pad and routing strip.Type: GrantFiled: August 10, 2004Date of Patent: November 14, 2006Assignee: Texas Instruments IncorporatedInventors: Navinchandra Kalidas, Jeremias P. Libres, Michael P. Pierce
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Patent number: 7033864Abstract: A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a plurality of metallic terminal pads (306) in locations matching the locations of the device contact pads, and further a plurality of grooves (310) and humps (311) distributed between the terminal pad locations, complementing the distribution of the terminal pads. Each bump is further attached to its matching terminal pad, respectively; the device is thus interconnected with the substrate and spaced apart by a gap (320). Adherent polymeric material (330) containing inorganic fillers fills the gap substantially without voids.Type: GrantFiled: September 3, 2004Date of Patent: April 25, 2006Assignee: Texas Instruments IncorporatedInventors: Jeremias P. Libres, Joel T. Medina, Mary C. Miller
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Patent number: 6936919Abstract: A packaged integrated circuit that includes a substrate 310; a chip 300 mounted on the substrate; and a heatsink 350 mounted on the chip. The heatsink has a spacer 360 attached to one of its surfaces to provide a standoff distance between the heatsink and the substrate. The substrate and the heatsink can include moats into which the spacer is adapted to fit. The moat can be a notch at the edge of the substrate or it can be a channel or depression in the substrate surface. The spacer can be made of a high-modulus or low-modulus material, or a combination of the two.Type: GrantFiled: August 21, 2002Date of Patent: August 30, 2005Assignee: Texas Instruments IncorporatedInventors: Shih-Fang Chuang, Jeremias P. Libres
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Publication number: 20040036162Abstract: A packaged integrated circuit that includes a substrate 310; a chip 300 mounted on the substrate; and a heatsink 350 mounted on the chip. The heatsink has a spacer 360 attached to one of its surfaces to provide a standoff distance between the heatsink and the substrate. The substrate and the heatsink can include moats into which the spacer is adapted to fit. The moat can be a notch at the edge of the substrate or it can be a channel or depression in the substrate surface. The spacer can be made of a high-modulus or low-modulus material, or a combination of the two.Type: ApplicationFiled: August 21, 2002Publication date: February 26, 2004Inventors: Shih-Fang Chuang, Jeremias P. Libres
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Publication number: 20040037059Abstract: A packaged integrated circuit including a substrate 310 having first and second opposing surfaces, wherein the first surface has a central chip pad location and a peripheral area surrounding the chip pad location. At least a portion of the peripheral area is covered by a spacer 330. An integrated circuit chip 300 is mounted on the chip pad location, and a heatsink 350 is mounted over the first surface of the substrate and attached to the chip and to the spacer. The spacer can be continuous and made to surround the chip pad location, or it can be discontinuous and placed at discrete locations in the peripheral area.Type: ApplicationFiled: August 21, 2002Publication date: February 26, 2004Inventors: Leon Stiborek, Jeremias P. Libres
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Patent number: 6432749Abstract: Methods for fabricating plastic molded thermally enhanced flip chip packages in which the heat spreaders are assembled in strip format is disclosed, including the first step of providing the heat spreader strip. Inclusion of heat spreaders in strip format allows better automation of the molding process using equipment and fabrication technology known in the industry, and provides a cost effective solution to assembly of high density area array packages. The design of heat spreaders include reduced cross section connecting straps which are readily severed and leave only a small plastic to metal interface for ingress of contamination. Further the designs comprehend either embedded or exposed heat spreaders with methods to hold securely during the molding process.Type: GrantFiled: August 22, 2000Date of Patent: August 13, 2002Assignee: Texas Instruments IncorporatedInventor: Jeremias P. Libres
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Patent number: 6214273Abstract: An improved mold system (20) is provided. The mold system (20) includes a mold (30) having a mold cavity (28). A pot (22) is connected to the mold cavity (28) through a boomerang runner system (24). The boomerang runner system may include a boomerang passage (25) having an inner curvilinear surface (44) and an outer curvilinear surface (42).Type: GrantFiled: November 10, 1998Date of Patent: April 10, 2001Assignee: Texas Instruments IncorporatedInventors: Chee Tay Liang, Jeremias P. Libres, Julius Lim, Jin Sin Sai, Chee Moon Ow, Mario A. Bolanos-Avila
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Patent number: 6071457Abstract: An improved mold system (20) is provided. The mold system (20) includes a mold (30) having at least one mold cavity (28). A pot (22) is connected to each of the mold cavities (28) through a runner system (24). A bellows container (50) containing a molding material (60) is disposed with the pot (22). A plunger (31) applies a compressive load to the molding material (60) contained with the bellows container (50) to force the molding material (60) through the runner system (24) into the mold cavities (28).Type: GrantFiled: September 24, 1998Date of Patent: June 6, 2000Assignee: Texas Instruments IncorporatedInventors: George A. Bednarz, Jeremias P. Libres, Subramanian Krishnamurthy, Thongioem Phanatnok
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Patent number: 5644168Abstract: A semiconductor package which comprises a lead frame, a semiconductor chip secured to the lead frame and a mold composition encasing the lead frame and the semiconductor chip has a filler of ceramic particles. Each of the ceramic particles, preferably silica or alumina, has macroscopic pores of sufficient size to receive a resin binder therein, the pores extending from the surface of the particle to the particle interior. A permanently hardenable composition adherable to the ceramic particles preferably an epoxy cresol novolac, extends around the ceramic particles and into the pores. The ceramic particles are formed by providing ceramic particles having a macroscopically smooth surface and subjecting the surfaces of the particles to a composition capable of removing portions of the particles, preferably hydrofluoric acid, while agitating the particles to form the pores.Type: GrantFiled: May 3, 1995Date of Patent: July 1, 1997Assignee: Texas Instruments IncorporatedInventors: Jeremias P. Libres, Abbas I. Attarwala, Mario A. Bolanos, Jimmy Liang, Indran B. Nair