Patents by Inventor Jeremy C. Andrus
Jeremy C. Andrus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11940931Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.Type: GrantFiled: January 5, 2021Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
-
Patent number: 11860796Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: GrantFiled: August 9, 2021Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Jeremy C. Andrus, Joseph R. Auricchio, Russell A. Blaine, Daniel A. Chimene, Simon M. Douglas, Landon J. Fuller, Yevgen Goryachok, John K. Kim-Biggs, Arnold S. Liu, James M. Magee, Daniel A. Steffen, Roberto G. Yepez
-
Patent number: 11748468Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.Type: GrantFiled: October 8, 2021Date of Patent: September 5, 2023Assignee: Apple Inc.Inventors: Bernard J. Semeria, Devon S. Andrade, Jeremy C. Andrus, Ahmed Bougacha, Peter Cooper, Jacques Fortier, Louis G. Gerbarg, James H. Grosbach, Robert J. McCall, Daniel A. Steffen, Justin R. Unger
-
Patent number: 11675919Abstract: Techniques are disclosed relating to securely storing data at a computing device that is managed by an external entity. In some embodiments, a computing device maintains a first file system volume having data that is accessible to a user of the computing device and that is not managed by an entity external to the computing device. The computing device receives, from the entity external, a first request to configure the computing device to store data that is accessible to the user and managed by the external entity. In response to the first request, the computing device creates a second distinct file system volume to store the data managed by the external entity. In response to a second request from the external entity, the computing device subsequently removes the second file system volume.Type: GrantFiled: November 13, 2019Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Ananthakrishna Ramesh, Andrew S. Terry, Wade Benson, Jeremy C. Andrus
-
Patent number: 11579934Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: March 22, 2021Date of Patent: February 14, 2023Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
-
Patent number: 11422857Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.Type: GrantFiled: May 22, 2020Date of Patent: August 23, 2022Assignee: Apple Inc.Inventors: Kushal Dalmia, Jeremy C. Andrus, Daniel A. Chimene, Nigel R. Gamble, James M. Magee, Daniel A. Steffen
-
Publication number: 20220027452Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.Type: ApplicationFiled: October 8, 2021Publication date: January 27, 2022Applicant: Apple Inc.Inventors: Bernard J. Semeria, Devon S. Andrade, Jeremy C. Andrus, Ahmed Bougacha, Peter Cooper, Jacques Fortier, Louis G. Gerbarg, James H. Grosbach, Robert J. McCall, Daniel A. Steffen, Justin R. Unger
-
Publication number: 20210365389Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Jeremy C. ANDRUS, Joseph R. Auricchio, Russell A. BLAINE, Daniel A. CHIMENE, Simon M. DOUGLAS, Landon J. FULLER, Yevgen GORYACHOK, John K. KIM-BIGGS, Arnold S. LIU, James M. MAGEE, Daniel A. STEFFEN, Roberto G. YEPEZ
-
Publication number: 20210318909Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: March 22, 2021Publication date: October 14, 2021Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
-
Patent number: 11144631Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.Type: GrantFiled: August 13, 2019Date of Patent: October 12, 2021Assignee: Apple Inc.Inventors: Bernard J. Semeria, Devon S. Andrade, Jeremy C. Andrus, Ahmed Bougacha, Peter Cooper, Jacques Fortier, Louis G. Gerbarg, James H. Grosbach, Robert J. McCall, Daniel A. Steffen, Justin R. Unger
-
Patent number: 11093601Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.Type: GrantFiled: October 25, 2019Date of Patent: August 17, 2021Assignee: Apple Inc.Inventors: Bernard J. Semeria, Devon S. Andrade, Jeremy C. Andrus, Ahmed Bougacha, Peter Cooper, Jacques Fortier, Louis G. Gerbarg, James H. Grosbach, Robert J. McCall, Daniel A. Steffen, Justin R. Unger
-
Patent number: 11086800Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.Type: GrantFiled: May 22, 2020Date of Patent: August 10, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, Joseph R. Auricchio, Russell A. Blaine, Daniel A. Chimene, Simon M. Douglas, Landon J. Fuller, Yevgen Goryachok, John K. Kim-Biggs, Arnold S. Liu, James M. Magee, Daniel A. Steffen, Roberto G. Yepez
-
Patent number: 11080095Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: August 3, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
-
Patent number: 11048562Abstract: Techniques are disclosed relating to efficiently handling execution of multiple threads to perform various actions. In some embodiments, an application instantiates a queue and a synchronization primitive. The queue maintains a set of work items to be operated on by a thread pool maintained by a kernel. The synchronization primitive controls access to the queue by a plurality of threads including threads of the thread pool. In such an embodiment, a first thread of the application enqueues a work item in the queue and issues a system call to the kernel to request that the kernel dispatch a thread of the thread pool to operate on the first work item. In various embodiments, the dispatched thread is executable to acquire the synchronization primitive, dequeue the work item, and operate on it.Type: GrantFiled: December 8, 2017Date of Patent: June 29, 2021Assignee: Apple Inc.Inventors: Daniel A. Steffen, Pierre Habouzit, Daniel A. Chimene, Jeremy C. Andrus, James M. Magee, Puja Gupta
-
Publication number: 20210157748Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.Type: ApplicationFiled: January 5, 2021Publication date: May 27, 2021Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
-
Patent number: 10956220Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: March 23, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
-
Patent number: 10901920Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.Type: GrantFiled: April 10, 2019Date of Patent: January 26, 2021Assignee: Apple Inc.Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
-
Patent number: 10891369Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.Type: GrantFiled: October 25, 2019Date of Patent: January 12, 2021Assignee: Apple Inc.Inventors: Bernard J. Semeria, Devon S. Andrade, Jeremy C. Andrus, Ahmed Bougacha, Peter Cooper, Jacques Fortier, Louis G. Gerbarg, James H. Grosbach, Robert J. McCall, Daniel A. Steffen, Justin R. Unger
-
Patent number: 10884811Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: January 5, 2021Assignee: Apple Inc.Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
-
Publication number: 20200379804Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Kushal Dalmia, Jeremy C. Andrus, Daniel A. Chimene, Nigel R. Gamble, James M. Magee, Daniel A. Steffen