Abstract: A system and method for preventing time-walking in a digital switching network when switching from a first clock to a second clock. The first and second clock can be identical in frequency and independent in phase, where the highest resolution frequency available is that of said first and second clock. The system can include a clock divider selection circuit, an enhanced digital phase aligner, and a clock select control circuit. The clock divider selection circuit can output an on-line divided clock and an off-line clock to the enhanced digital phase aligner. The enhanced digital phase aligner can sample the on-line divided clock with four phases of the off-line clock and output an off-line divided clock which is time shifted such that the off-line divided clock is in phase with the on-line divided clock within plus or minus one-half the clock period of the off-line clock.