Abstract: In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.

Abstract: In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.

Abstract: Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.

Abstract: A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

Abstract: Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.

Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Abstract: A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a damascene process flow. The semiconductor structure includes a substrate having a dielectric layer followed by the diamond-like carbon layer on a surface thereof. The diamond-like carbon layer is used as a hard-mask for forming conductive metal features from grown substrate material that fills a plurality of openings in the substrate, therein forming a semiconductor island structure, The semiconductor structure has a planar surface at the diamond-like carbon layer and the grown substrate material, whereby the diamond-like carbon polish-stop layer allows for over-planarization of the semiconductor island structure to provide an improved planar surface having a sufficient decrease in topography.

Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Abstract: A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation. The data communication system further includes a central data path in data communication for transferring data with the plurality of data paths.

Abstract: A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver.

Abstract: A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area.

Abstract: A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area.

Abstract: A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line.

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer.

Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography.

Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography.

Abstract: A method for making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer; depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenches through the one of the doped layer and the undoped porous oxide layer, the nitride layer, and the oxide layer, depositing an undoped oxide layer to fill the trenches, and patterning the undoped oxide by chemical mechanical polishing (CMP).