Abstract: A system for predicting latency of at least one variable-latency instruction, wherein a microprocessor includes at least one pipeline, the at least one pipeline having an instruction stream. The microprocessor is configured to issue at least one dependent instruction, execute the at least one pipeline to serve at least one variable-latency instruction, generate a result of the at least one variable-latency instruction, and serve the at least one dependent instruction by using the result of the at least one variable-latency instruction.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.

Abstract: Techniques for transitioning between code-based and data-based execution forms (or models) are disclosed. The techniques can be used to improve the performance of computing systems by allowing the execution to transition from one of the execution models to another one of the execution models that may be more suitable for carrying out the execution or effective processing of information in a computing system or environment. The techniques also allow switching back to the previous execution model when that previous model is more suitable than the execution model currently being used. In other words, the techniques allow transitioning (or switching) back and forth between a data-based and code-based execution (or information processing) models.

Abstract: Techniques for transitioning between code-based and data-based execution forms (or models) are disclosed. The techniques can be used to improve the performance of computing systems by allowing the execution to transition from one of the execution models to another one of the execution models that may be more suitable for carrying out the execution or effective processing of information in a computing system or environment. The techniques also allow switching back to the previous execution model when that previous model is more suitable than the execution model currently being used. In other words, the techniques allow transitioning (or switching) back and forth between a data-based and code-based execution (or information processing) models.

Abstract: Methods and an apparatus for data sorting is provided. Keys are derived from a data set and a mapping function is obtained for sorting the data set in accordance with the mapping function. A wide key sort on the keys is performed over a plurality of distributed nodes using the mapping function, resulting in sorted lists of rows from the data set produced in parallel from the nodes with each row associated with a unique one of the keys pushed to a stack machine. The sort process is an ordered row traversal from the stack machine.

Abstract: Storage devices and components, including memory components (e.g., non-volatile memory) can be trained by executable code that facilitates and/or performs reads and/or write requests to one or more storage sub-modules of a storage component (e.g., memory configured on a memory channel) made up of multiple storage components (e.g., DIMMs). The executable code can also train multiple storage components at the same time and/or in parallel.

Abstract: Methods and an apparatus for data sorting is provided. Keys are derived from a data set and a mapping function is obtained for sorting the data set in accordance with the mapping function. A wide key sort on the keys is performed over a plurality of distributed nodes using the mapping function, resulting in sorted lists of rows from the data set produced in parallel from the nodes with each row associated with a unique one of the keys pushed to a stack machine. The sort process is an ordered row traversal from the stack machine.

Abstract: A system for predicting latency of at least one variable-latency instruction, wherein a microprocessor includes at least one pipeline, the at least one pipeline having an instruction stream. The microprocessor is configured to issue at least one dependent instruction, execute the at least one pipeline to serve at least one variable-latency instruction, generate a result of the at least one variable-latency instruction, and serve the at least one dependent instruction by using the result of the at least one variable-latency instruction.

Abstract: A source data set is processed to produce a symbol table and a distribution without using a tree construct or any tree-related processing. The symbol table and the distribution outputted for encoding the data set and decoding encoded versions of the data set.

Abstract: A source data set is processed to produce a symbol table and a distribution without using a tree construct or any tree-related processing. The symbol table and the distribution outputted for encoding the data set and decoding encoded versions of the data set.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.

Abstract: Errors that can be detected as a result of the mapping of transmission data from its physical form back to its logical form can be considered in addition to the errors detected by using an error detection technique (e.g., a conventional CRC technique), thereby allowing fewer error detection/recovery bits (error recovery data or bits) to be used as would be possible by using the error detection technique alone. In other words, less error recovery data would be needed to achieve a given level accuracy using conventional techniques. As a result, overhead associated with adding error detection/recovery bits can be reduced.

Abstract: Storage devices and components, including memory components (e.g., non-volatile memory) can be trained by executable code that facilitates and/or performs reads and/or write requests to one or more storage sub-modules of a storage component (e.g., memory configured on a memory channel) made up of multiple storage components (e.g., DIMMs). The executable code can also train multiple storage components at the same time and/or in parallel.

Abstract: Techniques for transitioning between code-based and data-based execution forms (or models) are disclosed. The techniques can be used to improve the performance of computing systems by allowing the execution to transition from one of the execution models to another one of the execution models that may be more suitable for carrying out the execution or effective processing of information in a computing system or environment. The techniques also allow switching back to the previous execution model when that previous model is more suitable than the execution model currently being used. In other words, the techniques allow transitioning (or switching) back and forth between a data-based and code-based execution (or information processing) models.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.