Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.

Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.

Abstract: An apparatus is provided. The apparatus includes a lasing element, a laser driver and logic. The laser driver is configured to drive the lasing element at multiple current levels, and the laser driver includes a switching network, multiple direct current (DC) loops, and an output circuit. The switching network receives a differential input signal, and each DC loop is coupled to the switching network. The output circuit is also coupled to the lasing element, and the logic is coupled to each of the DC current loops, where the logic selects one or more of the DC loops in each (of several) modes. Each mode generates one or more output lasing currents for the lasing element that corresponds to a one or more of the current levels in response to the differential input signal.

Abstract: An apparatus is provided. The apparatus includes a lasing element, a laser driver and logic. The laser driver is configured to drive the lasing element at multiple current levels, and the laser driver includes a switching network, multiple direct current (DC) loops, and an output circuit. The switching network receives a differential input signal, and each DC loop is coupled to the switching network. The output circuit is also coupled to the lasing element, and the logic is coupled to each of the DC current loops, where the logic selects one or more of the DC loops in each (of several) modes. Each mode generates one or more output lasing currents for the lasing element that corresponds to a one or more of the current levels in response to the differential input signal.

Abstract: In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry).

Abstract: In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry).

Abstract: A fly height controller (10FHC; 10FHC?) for controlling the fly height of a read/write head assembly (15) in a disk drive (20) is disclosed. A heat element resistor (30) is disposed within the read/write head assembly (15). The fly height controller (10FHC; 10FHC?) includes registers (32R, 32W) for storing digital data words corresponding to the desired drive levels to be applied to the heat element resistor (30) during read and write operations. The registers (32R, 32W) are selectively coupled to a steady-state digital-to-analog converter (DAC) (36), depending upon whether a read or write operation is occurring; the output of the steady-state DAC (36) is applied to a voltage driver (40), which in turn drives current into the heat element resistor (30). Overdrive and underdrive transistors (44P, 44N) are provided to overdrive and underdrive the input to the voltage driver (40) in transitions between read and write operations.

Abstract: A low-power solution for maintaining an amplifier common-mode output voltage, regardless of whether the amplifier is on or off, that does not degrade the performance of the amplifier through the use of a passgate in the signal path.

Abstract: A magnetic recording control circuit for controlling current through a magnetic recording head includes a switch network, a signal coupler, and a current reducer. The switch network is connected to first and second magnetic recording head node regions and includes first, second, third, and fourth switches each having a variable magnitude conduction path and a control region. The signal coupler includes an input region and a plurality of output regions each connected to the control region of a corresponding switch. The current reducer is connected to the first magnetic recording head node region and shunts current away from the signal coupler.

Abstract: A write driver, having a pair of head pins for connection to a write head, includes two push-pull buffer circuits connected respectively between first and second pull-up resistors and the control nodes of first and second upper drive transistors. The buffer circuits selectively charge and discharge the inherent capacitances of the upper drive transistors, thereby accelerating their turn on and turn off without diminishing head swing. Moreover, connecting the buffer circuits between the pull-up resistors and the upper transistors effectively isolates, or buffers, the pull-up resistors from the self-inductance voltages of the write head, reducing glitching in the write-head output signal.